<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/drivers/hwtracing, branch v5.10</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>coresight: cti: Initialize dynamic sysfs attributes</title>
<updated>2020-10-29T19:10:25+00:00</updated>
<author>
<name>Suzuki K Poulose</name>
<email>suzuki.poulose@arm.com</email>
</author>
<published>2020-10-29T16:45:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=80624263fa289b3416f7ca309491f1b75e579477'/>
<id>80624263fa289b3416f7ca309491f1b75e579477</id>
<content type='text'>
With LOCKDEP enabled, CTI driver triggers the following splat due
to uninitialized lock class for dynamically allocated attribute
objects.

[    5.372901] coresight etm0: CPU0: ETM v4.0 initialized
[    5.376694] coresight etm1: CPU1: ETM v4.0 initialized
[    5.380785] coresight etm2: CPU2: ETM v4.0 initialized
[    5.385851] coresight etm3: CPU3: ETM v4.0 initialized
[    5.389808] BUG: key ffff00000564a798 has not been registered!
[    5.392456] ------------[ cut here ]------------
[    5.398195] DEBUG_LOCKS_WARN_ON(1)
[    5.398233] WARNING: CPU: 1 PID: 32 at kernel/locking/lockdep.c:4623 lockdep_init_map_waits+0x14c/0x260
[    5.406149] Modules linked in:
[    5.415411] CPU: 1 PID: 32 Comm: kworker/1:1 Not tainted 5.9.0-12034-gbbe85027ce80 #51
[    5.418553] Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT)
[    5.426453] Workqueue: events amba_deferred_retry_func
[    5.433299] pstate: 40000005 (nZcv daif -PAN -UAO -TCO BTYPE=--)
[    5.438252] pc : lockdep_init_map_waits+0x14c/0x260
[    5.444410] lr : lockdep_init_map_waits+0x14c/0x260
[    5.449007] sp : ffff800012bbb720
...

[    5.531561] Call trace:
[    5.536847]  lockdep_init_map_waits+0x14c/0x260
[    5.539027]  __kernfs_create_file+0xa8/0x1c8
[    5.543539]  sysfs_add_file_mode_ns+0xd0/0x208
[    5.548054]  internal_create_group+0x118/0x3c8
[    5.552307]  internal_create_groups+0x58/0xb8
[    5.556733]  sysfs_create_groups+0x2c/0x38
[    5.561160]  device_add+0x2d8/0x768
[    5.565148]  device_register+0x28/0x38
[    5.568537]  coresight_register+0xf8/0x320
[    5.572358]  cti_probe+0x1b0/0x3f0

...

Fix this by initializing the attributes when they are allocated.

Fixes: 3c5597e39812 ("coresight: cti: Add connection information to sysfs")
Reported-by: Leo Yan &lt;leo.yan@linaro.org&gt;
Tested-by: Leo Yan &lt;leo.yan@linaro.org&gt;
Cc: Mike Leach &lt;mike.leach@linaro.org&gt;
Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Cc: stable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20201029164559.1268531-2-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With LOCKDEP enabled, CTI driver triggers the following splat due
to uninitialized lock class for dynamically allocated attribute
objects.

[    5.372901] coresight etm0: CPU0: ETM v4.0 initialized
[    5.376694] coresight etm1: CPU1: ETM v4.0 initialized
[    5.380785] coresight etm2: CPU2: ETM v4.0 initialized
[    5.385851] coresight etm3: CPU3: ETM v4.0 initialized
[    5.389808] BUG: key ffff00000564a798 has not been registered!
[    5.392456] ------------[ cut here ]------------
[    5.398195] DEBUG_LOCKS_WARN_ON(1)
[    5.398233] WARNING: CPU: 1 PID: 32 at kernel/locking/lockdep.c:4623 lockdep_init_map_waits+0x14c/0x260
[    5.406149] Modules linked in:
[    5.415411] CPU: 1 PID: 32 Comm: kworker/1:1 Not tainted 5.9.0-12034-gbbe85027ce80 #51
[    5.418553] Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT)
[    5.426453] Workqueue: events amba_deferred_retry_func
[    5.433299] pstate: 40000005 (nZcv daif -PAN -UAO -TCO BTYPE=--)
[    5.438252] pc : lockdep_init_map_waits+0x14c/0x260
[    5.444410] lr : lockdep_init_map_waits+0x14c/0x260
[    5.449007] sp : ffff800012bbb720
...

[    5.531561] Call trace:
[    5.536847]  lockdep_init_map_waits+0x14c/0x260
[    5.539027]  __kernfs_create_file+0xa8/0x1c8
[    5.543539]  sysfs_add_file_mode_ns+0xd0/0x208
[    5.548054]  internal_create_group+0x118/0x3c8
[    5.552307]  internal_create_groups+0x58/0xb8
[    5.556733]  sysfs_create_groups+0x2c/0x38
[    5.561160]  device_add+0x2d8/0x768
[    5.565148]  device_register+0x28/0x38
[    5.568537]  coresight_register+0xf8/0x320
[    5.572358]  cti_probe+0x1b0/0x3f0

...

Fix this by initializing the attributes when they are allocated.

Fixes: 3c5597e39812 ("coresight: cti: Add connection information to sysfs")
Reported-by: Leo Yan &lt;leo.yan@linaro.org&gt;
Tested-by: Leo Yan &lt;leo.yan@linaro.org&gt;
Cc: Mike Leach &lt;mike.leach@linaro.org&gt;
Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Cc: stable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20201029164559.1268531-2-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>coresight: Fix uninitialised pointer bug in etm_setup_aux()</title>
<updated>2020-10-29T19:10:25+00:00</updated>
<author>
<name>Mike Leach</name>
<email>mike.leach@linaro.org</email>
</author>
<published>2020-10-29T16:45:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=39a7661dcf655c8198fd5d72412f5030a8e58444'/>
<id>39a7661dcf655c8198fd5d72412f5030a8e58444</id>
<content type='text'>
Commit [bb1860efc817] changed the sink handling code introducing an
uninitialised pointer bug. This results in the default sink selection
failing.

Prior to commit:

static void etm_setup_aux(...)

&lt;snip&gt;
        struct coresight_device *sink;
&lt;snip&gt;

        /* First get the selected sink from user space. */
        if (event-&gt;attr.config2) {
                id = (u32)event-&gt;attr.config2;
                sink = coresight_get_sink_by_id(id);
        } else {
                sink = coresight_get_enabled_sink(true);
        }
&lt;ctd&gt;

*sink always initialised - possibly to NULL which triggers the
automatic sink selection.

After commit:

static void etm_setup_aux(...)

&lt;snip&gt;
        struct coresight_device *sink;
&lt;snip&gt;

        /* First get the selected sink from user space. */
        if (event-&gt;attr.config2) {
                id = (u32)event-&gt;attr.config2;
                sink = coresight_get_sink_by_id(id);
        }
&lt;ctd&gt;

*sink pointer uninitialised when not providing a sink on the perf command
line. This breaks later checks to enable automatic sink selection.

Fixes: bb1860efc817 ("coresight: etm: perf: Sink selection using sysfs is deprecated")
Signed-off-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20201029164559.1268531-3-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit [bb1860efc817] changed the sink handling code introducing an
uninitialised pointer bug. This results in the default sink selection
failing.

Prior to commit:

static void etm_setup_aux(...)

&lt;snip&gt;
        struct coresight_device *sink;
&lt;snip&gt;

        /* First get the selected sink from user space. */
        if (event-&gt;attr.config2) {
                id = (u32)event-&gt;attr.config2;
                sink = coresight_get_sink_by_id(id);
        } else {
                sink = coresight_get_enabled_sink(true);
        }
&lt;ctd&gt;

*sink always initialised - possibly to NULL which triggers the
automatic sink selection.

After commit:

static void etm_setup_aux(...)

&lt;snip&gt;
        struct coresight_device *sink;
&lt;snip&gt;

        /* First get the selected sink from user space. */
        if (event-&gt;attr.config2) {
                id = (u32)event-&gt;attr.config2;
                sink = coresight_get_sink_by_id(id);
        }
&lt;ctd&gt;

*sink pointer uninitialised when not providing a sink on the perf command
line. This breaks later checks to enable automatic sink selection.

Fixes: bb1860efc817 ("coresight: etm: perf: Sink selection using sysfs is deprecated")
Signed-off-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20201029164559.1268531-3-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>coresight: add module license</title>
<updated>2020-10-29T07:36:41+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2020-10-26T16:01:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0f5cef2b2904b8d41d34ecb6c5d5bf2f00562b1b'/>
<id>0f5cef2b2904b8d41d34ecb6c5d5bf2f00562b1b</id>
<content type='text'>
When built as a loadable module, coresight now causes a warning about
missing license information.

WARNING: modpost: missing MODULE_LICENSE() in drivers/hwtracing/coresight/coresight.o

Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built as a module")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20201026160205.3704789-1-arnd@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When built as a loadable module, coresight now causes a warning about
missing license information.

WARNING: modpost: missing MODULE_LICENSE() in drivers/hwtracing/coresight/coresight.o

Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built as a module")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20201026160205.3704789-1-arnd@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_th: pci: Add Alder Lake CPU support</title>
<updated>2020-10-05T10:43:54+00:00</updated>
<author>
<name>Alexander Shishkin</name>
<email>alexander.shishkin@linux.intel.com</email>
</author>
<published>2020-10-05T07:13:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9f126c56b9d645e7014777d7d37d74eedc4e3137'/>
<id>9f126c56b9d645e7014777d7d37d74eedc4e3137</id>
<content type='text'>
This adds support for the Trace Hub in Alder Lake CPU.

Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-9-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds support for the Trace Hub in Alder Lake CPU.

Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-9-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_th: pci: Add Alder Lake-S support</title>
<updated>2020-10-05T10:43:54+00:00</updated>
<author>
<name>Alexander Shishkin</name>
<email>alexander.shishkin@linux.intel.com</email>
</author>
<published>2020-10-05T07:13:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=951e4d71a8fa84b76aff8181d288af025f250a3c'/>
<id>951e4d71a8fa84b76aff8181d288af025f250a3c</id>
<content type='text'>
This adds support for the Trace Hub in Alder Lake-S.

Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-8-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds support for the Trace Hub in Alder Lake-S.

Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-8-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>stm class: ftrace: Use different channel accroding to CPU</title>
<updated>2020-10-05T10:43:54+00:00</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-10-05T07:13:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b8f8534b10b6ee3cec5e49682d7e0c4796cdccea'/>
<id>b8f8534b10b6ee3cec5e49682d7e0c4796cdccea</id>
<content type='text'>
To avoid mixup of packets from differnt ftrace packets simultaneously,
use different channel for packets from different CPU.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-7-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To avoid mixup of packets from differnt ftrace packets simultaneously,
use different channel for packets from different CPU.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-7-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>stm class: ftrace: Enable supported trace export flag</title>
<updated>2020-10-05T10:43:54+00:00</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-10-05T07:13:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e8ecea3017385858be0ba5640b3b364586743c6b'/>
<id>e8ecea3017385858be0ba5640b3b364586743c6b</id>
<content type='text'>
Set flags for trace_export. Export function trace, event trace
and trace marker to stm.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Reviewed-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-6-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Set flags for trace_export. Export function trace, event trace
and trace marker to stm.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Reviewed-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-6-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>stm class: ftrace: Change dependency to TRACING</title>
<updated>2020-10-05T10:43:53+00:00</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-10-05T07:13:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=7b9749bd830848bca9179b0a16251ca3c36e82e6'/>
<id>7b9749bd830848bca9179b0a16251ca3c36e82e6</id>
<content type='text'>
We will support copying event trace to STM. Change
STM_SOURCE_FTRACE to depend on TRACING since we will
support multiple tracers.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Reviewed-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-2-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We will support copying event trace to STM. Change
STM_SOURCE_FTRACE to depend on TRACING since we will
support multiple tracers.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Reviewed-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-2-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register</title>
<updated>2020-09-28T17:47:42+00:00</updated>
<author>
<name>Sai Prakash Ranjan</name>
<email>saiprakash.ranjan@codeaurora.org</email>
</author>
<published>2020-09-28T16:35:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3477326277451000bc667dfcc4fd0774c039184c'/>
<id>3477326277451000bc667dfcc4fd0774c039184c</id>
<content type='text'>
In commit f188b5e76aae ("coresight: etm4x: Save/restore state
across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
value was saved in trcvmidcctlr0 state variable which is used to
store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then
same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
variable available for TRCVMIDCCTLR1, so use it.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-26-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In commit f188b5e76aae ("coresight: etm4x: Save/restore state
across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
value was saved in trcvmidcctlr0 state variable which is used to
store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then
same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
variable available for TRCVMIDCCTLR1, so use it.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-26-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>coresight: core: Allow the coresight core driver to be built as a module</title>
<updated>2020-09-28T17:47:42+00:00</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-09-28T16:35:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=8e264c52e1dab8a7c1e036222ef376c8920c3423'/>
<id>8e264c52e1dab8a7c1e036222ef376c8920c3423</id>
<content type='text'>
Enhance coresight developer's efficiency to debug coresight drivers.
- Kconfig becomes a tristate, to allow =m
- append -core to source file name to allow module to
  be called coresight by the Makefile
- modules can have only one init/exit, so we add the etm_perf
  register/unregister function calls to the core init/exit
  functions.
- add a MODULE_DEVICE_TABLE for autoloading on boot

Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Cc: Leo Yan &lt;leo.yan@linaro.org&gt;
Cc: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Cc: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Suzuki K Poulose &lt;Suzuki.Poulose@arm.com&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Tested-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@arm.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-25-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enhance coresight developer's efficiency to debug coresight drivers.
- Kconfig becomes a tristate, to allow =m
- append -core to source file name to allow module to
  be called coresight by the Makefile
- modules can have only one init/exit, so we add the etm_perf
  register/unregister function calls to the core init/exit
  functions.
- add a MODULE_DEVICE_TABLE for autoloading on boot

Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Cc: Leo Yan &lt;leo.yan@linaro.org&gt;
Cc: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Cc: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Suzuki K Poulose &lt;Suzuki.Poulose@arm.com&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Tested-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@arm.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-25-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
