linux-stable.git/drivers/gpu, branch v7.2.6

drm/xe/sysctrl: Read mailbox phase bit from hardware

2026-09-14T11:41:10+00:00

[ Upstream commit a62212b35a214c2ff3bd1c785a440d7ad8205ec9 ]

The mailbox PHASE bit in SYSCTRL_MB_CTRL is toggled per-message and
was tracked in software as sc->phase_bit, reset to 0 on error paths.
If the cached value ever drifts from what the hardware last saw, all
following messages carry the wrong phase and get silently misread by
firmware.

Drop the cache and read PHASE directly from SYSCTRL_MB_CTRL before
each frame instead, removing xe_sysctrl_mailbox_init() and its call
sites along with it.

Fixes: 1f95f618182b ("drm/xe/xe_sysctrl: Add System Controller mailbox communication support")
Signed-off-by: Anoop Vijay 
Reviewed-by: Umesh Nerlige Ramappa 
Reviewed-by: Rodrigo Vivi 
Link: https://patch.msgid.link/20260825172827.3801591-2-anoop.c.vijay@intel.com
Signed-off-by: Rodrigo Vivi 
(cherry picked from commit 04984fcdbf6876c940c01026a7404c1e9cc91ba7)
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Sasha Levin

drm/xe/xe_ras: Add support to get error counter value

2026-09-14T11:41:10+00:00

[ Upstream commit fe48a86980798ffc78c8713ec964877c8594610d ]

Add request/response structures and helper functions to query system
controller to get error counter value.

Reviewed-by: Raag Jadav 
Link: https://patch.msgid.link/20260618060633.2790109-10-riana.tauro@intel.com
Signed-off-by: Riana Tauro 
Stable-dep-of: a62212b35a21 ("drm/xe/sysctrl: Read mailbox phase bit from hardware")
Signed-off-by: Sasha Levin

drm/xe: Reject page faults from non-fault-mode scratch VMs

2026-09-14T11:41:09+00:00

[ Upstream commit 5e977521d21717edb8e91d004434697d6e3f248c ]

Having scratch enabled does not make a VM capable of handling recoverable
page faults. Allowing scratch VMs through the ASID lookup also admits
dma-fence mode VMs.

If such a VM faults on an already valid VMA, the handler reports success
without fixing the fault, causing the GPU to retry indefinitely.

Only allow fault-mode VMs through the ASID lookup. Fault-mode VMs using
scratch remain supported, while faults from 3D VMs are rejected.

Fixes: ad9843aac91a ("drm/xe/madvise: Implement purgeable buffer object support")
Cc: Matthew Brost 
Cc: Thomas Hellström 
Cc: Himal Prasad Ghimiray 
Suggested-by: Matthew Brost 
Signed-off-by: Arvind Yadav 
Reviewed-by: Matthew Brost 
Signed-off-by: Matthew Brost 
Link: https://patch.msgid.link/20260820065445.567228-1-arvind.yadav@intel.com
(cherry picked from commit bfb24a06405b652d37831f3fb66b71d33a6605de)
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Sasha Levin

drm/xe/xe_gt_idle: Add CCS to the powergating info print

2026-09-14T11:41:09+00:00

[ Upstream commit 369ba0d1efe91cccabe98ae53c53b7425f327edf ]

While reading the main GT powergating info from debugfs, include both
RCS and CCS engine masks.

Fixes: 0914c1e45d3a1 ("drm/xe/xe_gt_idle: add debugfs entry for powergating info")
Signed-off-by: Balasubramani Vivekanandan 
Link: https://patch.msgid.link/20260819073457.1812722-2-balasubramani.vivekanandan@intel.com
Reviewed-by: Matt Roper 
Signed-off-by: Matt Roper 
(cherry picked from commit 8899e413c5ab85443ec9bbc50cffe924c6b596de)
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Sasha Levin

drm/xe: Do not apply WA 14025883347 to media 3503

2026-09-14T11:41:09+00:00

[ Upstream commit f0feab6e9e008faa406d189fb40cb7ab1bed420a ]

The database was updated and the WA is no longer listed as applicable
to media 3503, so don't enable it there.

Fixes: c57db41b8d2c ("drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on reset")
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Sk Anirban 
Cc: Badal Nilawar 
Cc: Matt Roper 
Reviewed-by: Matt Roper 
Link: https://patch.msgid.link/20260818213520.283063-1-daniele.ceraolospurio@intel.com
(cherry picked from commit fae59d5de5de39bc51ac2839f74970312e0c8905)
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Sasha Levin

drm/xe: don't WARN on kernel job timeout when device already wedged

2026-09-14T11:41:00+00:00

[ Upstream commit 13087ad7817e6e5f210064518bfc4d6d58a9c2f3 ]

igt@xe_wedged@wedged-at-any-timeout wedges the device in mode 2
(UPON_ANY_HANG_NO_RESET) and then rebinds the driver. During unbind,
a GSC proxy kernel submission can still time out; with the device wedged
and the GuC CT stopped it can never complete, so its kernel job times out.

  Tile0: GT1: Kernel-submitted job timed out
  WARNING: drivers/gpu/drm/xe/xe_guc_submit.c:...
	   at guc_exec_queue_timedout_job()
  Workqueue: gt-ordered-wq drm_sched_job_timedout

Killed queues skip guc_submit_hint_wedged(), leaving 'wedged' false even
though the device is already wedged. The timeout handler then treats the
kernel queue timeout as unexpected and taints the kernel.

Honour an already-wedged device even for killed queues so the expected
teardown timeout no longer trips the WARN.

Fixes: 5a2f117a80c2 ("drm/xe: Do not wedge device on killed exec queues")
Cc: Matthew Brost 
Signed-off-by: Nitin Gote 
Reviewed-by: Tejas Upadhyay 
Link: https://patch.msgid.link/20260814074106.92670-2-nitin.r.gote@intel.com
Signed-off-by: Tejas Upadhyay 
(cherry picked from commit a1c1dbd0f047bb05de6aaf6abe9103031179bf19)
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Sasha Levin

drm/xe: tests: fix error message in xe_migrate_sanity_test()

2026-09-14T11:40:53+00:00

[ Upstream commit 3d318fe4e99a627aa3c2980699e2e9f13ad18516 ]

This is supposed to print the error code but there is a copy and
paste bug so it prints "bo" instead of "err".

Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Dan Carpenter 
Link: https://patch.msgid.link/an1tu0z3T-qX1ogn@stanley.mountain
Signed-off-by: Rodrigo Vivi 
(cherry picked from commit 28a4198c52a1468fc1b620a9837557ea1dc1766d)
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Sasha Levin

drm/amd/pm: silence uninitialized variable warnings

2026-09-14T11:40:42+00:00

[ Upstream commit b4cb43789b6ac0f25fc0d9b21c5e7a6225cf6a31 ]

Smatch complains that:

    drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu15/smu_v15_0_8_ppt.c:1964
    smu_v15_0_8_set_performance_level() error: uninitialized symbol 'ret'.

In this line there is an "if (ret)" condition where "ret" is either
zero or uninitialized.  Initialize "ret" at the start of the function to
avoid a potential uninitialized variable bug.  But also delete the
condition since it is never true.

Fixes: 422b399b09c7 ("drm/amd/pm: Add od_edit_dpm_table support")
Reviewed-by: Lijo Lazar 
Signed-off-by: Dan Carpenter 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amdgpu/gfx6: Use PFP on the compute queues too

2026-09-14T11:40:26+00:00

[ Upstream commit 60f20946cd318518ddc2c0da12103c666b2b9564 ]

On GFX6, the compute rings use the same CP path as
the graphics ring. The only difference is that they
don't support draw commands. (As opposed to GFX7 and
newer which have a separate command parser that is
called MEC for compute queues.)

This means that we have to take into consideration
that the PFP also exists on compute queues on GFX6:

Use PFP for register writes on both graphics and
compute queues.

In the pipeline sync, use the PFP to wait for the
previous fence (and not the ME) to prevent the PFP
from starting to execute the next submission while
the ME is still in the previous submission.

After a VM flush, emit PFP_SYNC_ME on compute
queues as well.

Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
Signed-off-by: Timur Kristóf 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amdgpu/gfx6: Fixup emitting SWITCH_BUFFER packets

2026-09-14T11:40:26+00:00

[ Upstream commit 7aac4242a11991d530eee3e141d6e445d5f11c22 ]

Implement the emit_switch_buffer() function instead of emitting
them duing emit_ib, emit_pipeline_sync and emit_vm_flush.

Note that it isn't necessary to emit these in both
emit_pipeline_sync() and emit_vm_flush() because
amdgpu_vm_flush() already calls these when calling
either of those functions.

Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
Signed-off-by: Timur Kristóf 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin