linux-stable.git/drivers/gpu/ipu-v3, branch linux-4.9.y

gpu: ipu-v3: Fix dev_dbg frequency output

2022-04-20T07:06:45+00:00

[ Upstream commit 070a88fd4a03f921b73a2059e97d55faaa447dab ]

This commit corrects the printing of the IPU clock error percentage if
it is between -0.1% to -0.9%. For example, if the pixel clock requested
is 27.2 MHz but only 27.0 MHz can be achieved the deviation is -0.8%.
But the fixed point math had a flaw and calculated error of 0.2%.

Before:
  Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
  IPU clock can give 27000000 with divider 10, error 0.2%
  Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU, 27000000Hz

After:
  Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
  IPU clock can give 27000000 with divider 10, error -0.8%
  Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU, 27000000Hz

Signed-off-by: Leo Ruan 
Signed-off-by: Mark Jonas 
Reviewed-by: Philipp Zabel 
Signed-off-by: Philipp Zabel 
Link: https://lore.kernel.org/r/20220207151411.5009-1-mark.jonas@de.bosch.com
Signed-off-by: Sasha Levin

gpu: ipu-v3: image-convert: Combine rotate/no-rotate irq handlers

2020-08-21T09:02:09+00:00

[ Upstream commit 0f6245f42ce9b7e4d20f2cda8d5f12b55a44d7d1 ]

Combine the rotate_irq() and norotate_irq() handlers into a single
eof_irq() handler.

Signed-off-by: Steve Longerbeam 
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin

gpu: ipu-v3: ipu-ic: Fix saturation bit offset in TPMEM

2019-08-04T07:33:30+00:00

commit 3d1f62c686acdedf5ed9642b763f3808d6a47d1e upstream.

The saturation bit was being set at bit 9 in the second 32-bit word
of the TPMEM CSC. This isn't correct, the saturation bit is bit 42,
which is bit 10 of the second word.

Fixes: 1aa8ea0d2bd5d ("gpu: ipu-v3: Add Image Converter unit")

Signed-off-by: Steve Longerbeam 
Reviewed-by: Philipp Zabel 
Cc: stable@vger.kernel.org
Signed-off-by: Philipp Zabel 
Signed-off-by: Greg Kroah-Hartman

gpu: ipu-v3: dp: fix CSC handling

2019-05-16T17:43:43+00:00

[ Upstream commit d4fad0a426c6e26f48c9a7cdd21a7fe9c198d645 ]

Initialize the flow input colorspaces to unknown and reset to that value
when the channel gets disabled. This avoids the state getting mixed up
with a previous mode.

Also keep the CSC settings for the background flow intact when disabling
the foreground flow.

Root-caused-by: Jonathan Marek 
Signed-off-by: Lucas Stach 
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin

gpu: ipu-v3: Fix CSI offsets for imx53

2019-03-23T12:19:41+00:00

[ Upstream commit bb867d219fda7fbaabea3314702474c4eac2b91d ]

The CSI offsets are wrong for both CSI0 and CSI1. They are at
physical address 0x1e030000 and 0x1e038000 respectively.

Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")

Signed-off-by: Steve Longerbeam 
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin

gpu: ipu-v3: Fix i.MX51 CSI control registers offset

2019-03-23T12:19:41+00:00

[ Upstream commit 2c0408dd0d8906b26fe8023889af7adf5e68b2c2 ]

The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.

Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")

Signed-off-by: Alexander Shiyan 
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin

gpu: ipu-v3: image-convert: Prevent race between run and unprepare

2019-02-12T18:44:51+00:00

[ Upstream commit 819bec35c8c9706185498c9222bd244e0781ad35 ]

Prevent possible race by parallel threads between ipu_image_convert_run()
and ipu_image_convert_unprepare(). This involves setting ctx->aborting
to true unconditionally so that no new job runs can be queued during
unprepare, and holding the ctx->aborting flag until the context is freed.

Note that the "normal" ipu_image_convert_abort() case (e.g. not during
context unprepare) should clear the ctx->aborting flag after aborting
any active run and clearing the context's pending queue. This is because
it should be possible to continue to use the conversion context and queue
more runs after an abort.

Signed-off-by: Steve Longerbeam 
Tested-by: Philipp Zabel 
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin

gpu: ipu-v3: Fix CSI selection for VDIC

2018-11-10T15:42:48+00:00

[ Upstream commit b7dfee2433576f1f030cb84cdb04b70f36554992 ]

The description of the CSI_SEL bit in the i.MX6 reference manual is
incorrect. It states "This bit defines which CSI is the input to the
IC. This bit is effective only if IC_INPUT is bit cleared".

From experiment it was found this is in fact not correct. The CSI_SEL
bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the
IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC
ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC
receives from in that case.

Signed-off-by: Marek Vasut 
Signed-off-by: Steve Longerbeam 
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin

gpu: ipu-v3: csi: pass back mbus_code_to_bus_cfg error codes

2018-09-26T06:36:38+00:00

[ Upstream commit d36d0e6309dd8137cf438cbb680e72eb63c81425 ]

mbus_code_to_bus_cfg() can fail on unknown mbus codes; pass back the
error to the caller.

Signed-off-by: Enrico Scholz 
Signed-off-by: Jan Luebbe 
[p.zabel@pengutronix.de - renamed rc to ret for consistency]
Signed-off-by: Philipp Zabel 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

gpu: ipu-v3: Use ERR_CAST instead of ERR_PTR(PTR_ERR())

2016-10-17T06:21:53+00:00

Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...)).

Generated by: scripts/coccinelle/api/err_cast.cocci

Signed-off-by: Wei Yongjun 
Signed-off-by: Philipp Zabel