linux-stable.git/drivers/gpu/drm, branch v3.12.6

drm/i915/vlv: fix up broken precision in vlv_crtc_clock_get

2013-12-20T15:49:10+00:00

commit 662c6ecbcdca1fe8a5402f6c83d98d242917a043 upstream.

With some divider values we end up with the wrong result.  So remove the
intermediates (like Ville suggested in the first place) to get the right
answer.

Signed-off-by: Chris Wilson 
Signed-off-by: Jesse Barnes 
Signed-off-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Greg Kroah-Hartman

drm/i915/vlv: add VLV specific clock_get function v3

2013-12-20T15:49:10+00:00

commit acbec814a27f233b5ddb88a1bcaa2ac20daf64e0 upstream.

Calculation is a little different than other platforms.

v2: update to use port_clock instead
    rebase on top of Ville's changes
v3: update to new port_clock semantics - don't divide by
    pixel_multiplier (Ville)

References: https://bugs.freedesktop.org/show_bug.cgi?id=67345
Signed-off-by: Jesse Barnes 
Reviewed-by: Ville Syrjälä 
Signed-off-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Greg Kroah-Hartman

i915/vlv: untangle integrated clock source handling v4

2013-12-20T15:49:10+00:00

commit f60711666bcab6df2c6c91d851e07ed54088453c upstream.

The global integrated clock source bit resides in DPLL B on VLV, but we
were treating it as a per-pipe resource.  It needs to be set whenever
any PLL is active, so pull setting the bit out of vlv_update_pll and
into vlv_enable_pll.  Also add a vlv_disable_pll to prevent disabling it
when pipe B shuts down.

I'm guessing on the references here, I expect this to bite any config
where multiple displays are active or displays are moved from pipe to
pipe.

v2: re-add bits in vlv_update_pll to keep from confusing the state checker
v3: use enum pipe checks (Daniel)
    set CRI clock source early (Ville)
    consistently set CRI clock source everywhere (Ville)
v4: drop unnecessary setting of bit in vlv enable pll (Ville)

References: https://bugs.freedesktop.org/show_bug.cgi?id=67245
References: https://bugs.freedesktop.org/show_bug.cgi?id=69693
Signed-off-by: Jesse Barnes 
Reviewed-by: Ville Syrjälä 
[danvet: s/1/PIPE_B/]
Signed-off-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Greg Kroah-Hartman

drm/radeon/atom: fix bus probes when hw_i2c is set (v2)

2013-12-20T15:49:01+00:00

commit ffd3d3361d583cb73fa65a5fed3a196ba6f261bb upstream.

When probing the bus, we need to set the byte count
to 0 rather than 1.

v2: Don't count the first byte.

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=66241

Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman

drm/radeon: fixup bad vram size on SI

2013-12-20T15:49:01+00:00

commit 0ca223b029a261e82fb2f50c52eb85d510f4260e upstream.

Some boards seem to have garbage in the upper
16 bits of the vram size register.  Check for
this and clamp the size properly.  Fixes
boards reporting bogus amounts of vram.

Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman

drm/radeon: program DCE2 audio dto just like DCE3

2013-12-20T15:49:01+00:00

commit 55d4e020fb8ddd3896a8cd3351028f5c3a2c4bd3 upstream.

Seems to work like the DCE3 version despite what
the register spec says.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=71975

Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman

drm/radeon: fix typo in fetching mpll params

2013-12-20T15:49:00+00:00

commit 180f805f4f03b2894701f9831b4e96a308330b22 upstream.

Copy-paste typo.  Value should be 0-2, not 0-1.

Noticed-by: Sylvain BERTRAND 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman

drm/i915: use the correct force_wake function at the PC8 code

2013-12-20T15:49:00+00:00

commit a1216444283e81fd904593a4a77c90adfe5d14d1 upstream.

When I submitted the first patch adding these force wake functions,
Chris Wilson observed that I was using the wrong functions, so I sent
a second version of the patch to correct this problem. The problem is
that v1 was merged instead of v2.

I was able to notice the problem when running the
debugfs-forcewake-user subtest of pm_pc8 from intel-gpu-tools.

Signed-off-by: Paulo Zanoni 
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Daniel Vetter 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Fix pipe CSC post offset calculation

2013-12-20T15:48:58+00:00

commit 32cf0cb0294814cb1ee5d8727e9aac0e9aa80d2e upstream.

We were miscalculating the pipe CSC post offset for the full->limited
range conversion. The resulting post offset was double what it was
supposed to be, which caused blacks to come out grey when using
limited range output on HSW+.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71769
Tested-by: Lauri Mylläri 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Daniel Vetter 
Signed-off-by: Greg Kroah-Hartman

udl: fix issue with imported prime buffers

2013-12-20T15:48:49+00:00

commit 1d507b3af40a60e03a3bbc4c897fc2709c075d24 upstream.

5dc9e1e8 was a bit over-ambitious, and accidentially removed handling
for imported prime buffers.

Signed-off-by: Rob Clark 
Signed-off-by: Dave Airlie 
Cc: Thomas Meyer 
Signed-off-by: Greg Kroah-Hartman