linux-stable.git/drivers/gpu/drm/rockchip, branch linux-6.16.y

drm/rockchip: vop2: make vp registers nonvolatile

2025-09-09T17:02:16+00:00

[ Upstream commit a52dffaa46c2c5ff0b311c4dc1288581f7b9109e ]

Make video port registers nonvolatile. As DSP_CTRL register is written
to twice due to gamma LUT enable bit which is set outside of the main
DSP_CTRL initialization within atomic_enable (for rk356x case it is also
necessary to always disable gamma LUT before writing a new LUT) there is
a chance that DSP_CTRL value read-out in gamma LUT init/update code is
not the one which was written by the preceding DSP_CTRL initialization
code within atomic_enable. This might result in misconfigured DSP_CTRL
which leads to no visual output[1]. Since DSP_CTRL write takes effect
after VSYNC[1] the issue is not always present. When tested on Pinetab2
with kernel 6.14 it happenes only when DRM is compiled as a module[1].
In order to confirm that it is a timing issue I inserted 18ms udelay
before vop2_crtc_atomic_try_set_gamma in atomic enable and compiled DRM
as module - this has also fixed the issue.

[1] https://lore.kernel.org/linux-rockchip/562b38e5.a496.1975f09f983.Coremail.andyshrk@163.com/

Reported-by: Diederik de Haas 
Closes: https://lore.kernel.org/linux-rockchip/DAEVDSTMWI1E.J454VZN0R9MA@cknow.org/
Suggested-by: Andy Yan 
Signed-off-by: Piotr Zalewski 
Tested-by: Diederik de Haas 
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250706083629.140332-2-pZ010001011111@proton.me
Signed-off-by: Sasha Levin

drm/rockchip: vop2: Fix the update of LAYER/PORT select registers when there are multi display output on rk3588/rk3568

2025-08-15T14:38:44+00:00

[ Upstream commit 3e89a8c6835476aa782da80585dee9ddae651eea ]

The all video ports of rk3568/rk3588 share the same OVL_LAYER_SEL
and OVL_PORT_SEL registers, and the configuration of these two registers
can be set to take effect when the vsync signal arrives at a certain Video
Port.

If two threads for two display output choose to update these two registers
simultaneously to meet their own plane adjustment requirements(change plane
zpos or switch plane from one crtc to another), then no matter which Video
Port'svsync signal we choose to follow for these two registers, the display
output of the other Video Port will be abnormal.
This is because the configuration of this Video Port does not take
effect at the right time (its configuration should take effect when its
VSYNC signal arrives).

In order to solve this problem, when performing plane migration or
change the zpos of planes, there are two things to be observed and
followed:

1. When a plane is migrated from one VP to another, the configuration of
the layer can only take effect after the Port mux configuration is
enabled.

2. When change the zpos of planes, we must ensure that the change for
the previous VP takes effect before we proceed to change the next VP.
Otherwise, the new configuration might overwrite the previous one for
the previous VP, or it could lead to the configuration of the previous
VP being take effect along with the VSYNC of the new VP.

This issue only occurs in scenarios where multi-display output is enabled.

Fixes: c5996e4ab109 ("drm/rockchip: vop2: Make overlay layer select register configuration take effect by vsync")
Signed-off-by: Andy Yan
Signed-off-by: Heiko Stuebner
Link: https://lore.kernel.org/r/20250421102156.424480-1-andyshrk@163.com
Signed-off-by: Sasha Levin

drm/rockchip: vop2: fail cleanly if missing a primary plane for a video-port

2025-08-15T14:38:44+00:00

[ Upstream commit f9f68bf1d0efeadb6c427c9dbb30f307a7def19b ]

Each window of a vop2 is usable by a specific set of video ports, so while
binding the vop2, we look through the list of available windows trying to
find one designated as primary-plane and usable by that specific port.

The code later wants to use drm_crtc_init_with_planes with that found
primary plane, but nothing has checked so far if a primary plane was
actually found.

For whatever reason, the rk3576 vp2 does not have a usable primary window
(if vp0 is also in use) which brought the issue to light and ended in a
null-pointer dereference further down.

As we expect a primary-plane to exist for a video-port, add a check at
the end of the window-iteration and fail probing if none was found.

Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
Reviewed-by: Andy Yan 
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250610212748.1062375-1-heiko@sntech.de
Signed-off-by: Sasha Levin

drm/rockchip: cleanup fb when drm_gem_fb_afbc_init failed

2025-08-15T14:38:36+00:00

[ Upstream commit 099593a28138b48feea5be8ce700e5bc4565e31d ]

In the function drm_gem_fb_init_with_funcs, the framebuffer (fb)
and its corresponding object ID have already been registered.

So we need to cleanup the drm framebuffer if the subsequent
execution of drm_gem_fb_afbc_init fails.

Directly call drm_framebuffer_put to ensure that all fb related
resources are cleanup.

Fixes: 7707f7227f09 ("drm/rockchip: Add support for afbc")
Signed-off-by: Andy Yan 
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250509031607.2542187-1-andyshrk@163.com
Signed-off-by: Sasha Levin

drm/rockchip: inno-hdmi: Fix video timing HSYNC/VSYNC polarity setting for rk3036

2025-05-04T10:40:53+00:00

The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed
from the HDMI protocol analyzer that the H/V front/back timing
output by RK3036 HDMI are currently not in line with the specifications.

Signed-off-by: Andy Yan 
Tested-by: Heiko Stuebner  #rk3036-kylin
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250422070455.432666-5-andyshrk@163.com

drm/rockchip: inno-hdmi: Simplify error handler with dev_err_probe

2025-05-04T10:40:52+00:00

Use dev_err_probe simplify the error handle.

Signed-off-by: Andy Yan 
Tested-by: Heiko Stuebner  #rk3036-kylin
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250422070455.432666-4-andyshrk@163.com

drm/rockchip: rk3066_hdmi: switch to drm bridge

2025-05-04T10:36:34+00:00

Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.

Note: I don't have the hardware to test this driver, so for now
I can only do the compilation test.

Signed-off-by: Andy Yan 
Tested-by: Heiko Stuebner  #rk3066-marsboard
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250428102309.1501986-1-andyshrk@163.com

drm/rockchip: add CONFIG_OF dependency

2025-05-01T11:01:47+00:00

DRM_DISPLAY_DP_AUX_BUS cannot be selected when CONFIG_OF is disabled:

WARNING: unmet direct dependencies detected for DRM_DISPLAY_DP_AUX_BUS
  Depends on [n]: HAS_IOMEM [=y] && DRM [=y] && OF [=n]
  Selected by [y]:
  - DRM_ROCKCHIP [=y] && HAS_IOMEM [=y] && DRM [=y] && ROCKCHIP_IOMMU [=y] && ROCKCHIP_ANALOGIX_DP [=y]

Rockchip platforms all depend on OF anyway, so add the dependency here
for compile testing.

Fixes: d7b4936b2bc0 ("drm/rockchip: analogix_dp: Add support to get panel from the DP AUX bus")
Signed-off-by: Arnd Bergmann 
Reviewed-by: Dmitry Baryshkov 
Acked-by: Andy Yan 
Signed-off-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250423164422.2793634-1-arnd@kernel.org

drm/rockchip: analogix_dp: Add support for RK3588

2025-04-20T22:27:10+00:00

RK3588 integrates the Analogix eDP 1.3 TX controller IP and the HDMI/eDP
TX Combo PHY based on a Samsung IP block. There are also two independent
eDP display interface with different address on RK3588 Soc.

The patch currently adds only the basic support, specifically RGB output
up to 4K@60Hz, without the tests for audio, PSR and other eDP 1.3 specific
features.

In additon, the above Analogix IP has always been utilized as eDP on
Rockchip platform, despite its capability to also support the DP v1.2.
Therefore, the newly added logs will contain the term 'edp' rather than
'dp'. And the newly added 'apb' reset control is to ensure the APB bus
of eDP controller works well on the RK3588 SoC.

Acked-by: Dmitry Baryshkov 
Signed-off-by: Damon Ding 
Link: https://lore.kernel.org/r/20250310104114.2608063-12-damon.ding@rock-chips.com
Signed-off-by: Dmitry Baryshkov

drm/rockchip: analogix_dp: Add support to get panel from the DP AUX bus

2025-04-20T22:27:10+00:00

Move drm_of_find_panel_or_bridge() a little later and combine it with
component_add() into a new function rockchip_dp_link_panel(). The function
will serve as done_probing() callback of devm_of_dp_aux_populate_bus(),
aiding to support for obtaining the eDP panel via the DP AUX bus.

If failed to get the panel from the DP AUX bus, it will then try the other
way to get panel information through the platform bus.

Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Damon Ding 
Reviewed-by: Douglas Anderson 
Link: https://lore.kernel.org/r/20250310104114.2608063-9-damon.ding@rock-chips.com
Signed-off-by: Dmitry Baryshkov