linux-stable.git/drivers/gpu/drm/msm/dsi, branch linux-4.6.y

drm/msm: update generated headers

2016-03-03T16:55:27+00:00

Pull in additional regs needed for a430, etc.

Signed-off-by: Rob Clark

drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()

2016-03-03T16:55:26+00:00

This fixes the following build failure:

drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.o: In function `msm_dsi_pll_28nm_8960_init':
dsi_pll_28nm.c:(.text+0x1198): multiple definition of `msm_dsi_pll_28nm_8960_init'
drivers/gpu/drm/msm/dsi/pll/dsi_pll.o:dsi_pll.c:(.text+0x0): first defined here

Signed-off-by: Luis Henriques 
Acked-by: Archit Taneja 
Signed-off-by: Rob Clark

drm/msm/dsi: Parse DSI lanes via DT

2016-03-03T16:55:20+00:00

The DSI driver is currently unaware of how the DSI physical data lanes
are mapped to the logical lanes provided by the DSI controller.

Create a DT binding "qcom,data-lane-map" that provides this information
on a given platform.

The MSM DSI controller is restricted in terms of what all mappings
it can support. The lane polarity is fixed for all the lanes, the clock
lanes are fixed, and the data lanes can be swapped among each other only
for a few combinations. Apply these restrictions when we parse the DT
data.

Cc: devicetree@vger.kernel.org
Cc: Rob Herring 
Cc: Tomi Valkeinen 

Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark 
Acked-by: Rob Herring

drm/msm/dsi: Drop VDD regulator for MSM8916

2016-03-02T21:19:47+00:00

VDD regulator input was specified for MSM8916. It turns our that this
regulator is used for the display panels used on MSM8916 platforms, but
not the DSI controller itself. Drop this regulator from the list.

Reported-by: Vinay Simha 
Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark

drm/msm/dsi: Remove incorrect warning on host attach

2016-03-02T21:19:46+00:00

With the implementation of of_graph parsing, it isn't any longer
necessary for msm_host->device node to be same as dsi->dev.of_node. This
only holds true when the connected device is also a child of the dsi_host.

In the case of external bridge chips belonging to a different control
bus, these are guaranteed to be different.

Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark

drm/msm/dsi: Added missing mutex_unlock

2015-12-14T16:50:57+00:00

in case of failed to get iova, function was returning without releasing
the mutex. Added it.

Signed-off-by: Saurabh Sengar 
Signed-off-by: Rob Clark

drm/msm/dsi: Enable MMSS SPFB port via syscon

2015-12-14T15:40:50+00:00

For DSIv2 to work, we need to enable MMSS_AHB_ARB_MASTER_PORT in
MMSS_SFPB. We enable the required bitfield by retrieving MMSS_SFPB
regmap pointer via syscon.

Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark

drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2

2015-12-14T15:40:45+00:00

We currently use iommu allocated DMA buffers for sending DSI commands.
DSIv2 doesn't have a port connected to the MDP iommu. Therefore, it
can't use iommu allocated buffers to fetch DSI commands.

Use a regular contiguous DMA buffer if we are DSIv2.

Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark

drm/msm/dsi: Add dsi_cfg for APQ8064

2015-12-14T15:40:40+00:00

Add a dsi_cfg entry for APQ8064. Since this is the first DSIv2 chip to
be supported, add a list of bus clocks that are required by the DSIv2
block.

Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark

drm/msm/dsi: Set up link clocks for DSIv2

2015-12-14T15:40:35+00:00

DSIv2 (DSI on older A family chips) has slightly different link clock
requirements.

First, we have an extra clock called src_clk (with a dedicated RCG).
This is required by the DSI controller to process the pixel data
coming from MDP. It needs to be set at the rate "pclk * bytes_per_pixel".

We also need to explicitly configure esc_clk. On DSI6G chips, we don't
need to set a rate to esc_clk because its RCG is always sourced from
crystal clock (19.2 Mhz in all cases), which is within the escape clock
frequency range in the mipi DSI spec. For chips with DSIv2, the crystal
clock rate may not be within the required range (27Mhz on APQ8064).
Therefore, we derive it from the DSI byte clock. We calculate an esc_clck
rate that is within the mipi spec and also divisible by the byte clock
rate.

When setting rate and enabling the link clocks, we make sure that byte_clk
is configured before esc_clk, and src_clk before pixel_clk. We create two
different link_enable funcs for DSI6G and DSIv2 since the sequences are
different.

We also obtain two extra source clocks (dsi_src_clk and esc_src_clk) and
set their parent to the clocks provided by DSI PLL.

Signed-off-by: Archit Taneja 
Signed-off-by: Rob Clark