linux-stable.git/drivers/gpu/drm/amd, branch v7.2.6

drm/amd/pm: silence uninitialized variable warnings

2026-09-14T11:40:42+00:00

[ Upstream commit b4cb43789b6ac0f25fc0d9b21c5e7a6225cf6a31 ]

Smatch complains that:

    drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu15/smu_v15_0_8_ppt.c:1964
    smu_v15_0_8_set_performance_level() error: uninitialized symbol 'ret'.

In this line there is an "if (ret)" condition where "ret" is either
zero or uninitialized.  Initialize "ret" at the start of the function to
avoid a potential uninitialized variable bug.  But also delete the
condition since it is never true.

Fixes: 422b399b09c7 ("drm/amd/pm: Add od_edit_dpm_table support")
Reviewed-by: Lijo Lazar 
Signed-off-by: Dan Carpenter 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amdgpu/gfx6: Use PFP on the compute queues too

2026-09-14T11:40:26+00:00

[ Upstream commit 60f20946cd318518ddc2c0da12103c666b2b9564 ]

On GFX6, the compute rings use the same CP path as
the graphics ring. The only difference is that they
don't support draw commands. (As opposed to GFX7 and
newer which have a separate command parser that is
called MEC for compute queues.)

This means that we have to take into consideration
that the PFP also exists on compute queues on GFX6:

Use PFP for register writes on both graphics and
compute queues.

In the pipeline sync, use the PFP to wait for the
previous fence (and not the ME) to prevent the PFP
from starting to execute the next submission while
the ME is still in the previous submission.

After a VM flush, emit PFP_SYNC_ME on compute
queues as well.

Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
Signed-off-by: Timur Kristóf 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amdgpu/gfx6: Fixup emitting SWITCH_BUFFER packets

2026-09-14T11:40:26+00:00

[ Upstream commit 7aac4242a11991d530eee3e141d6e445d5f11c22 ]

Implement the emit_switch_buffer() function instead of emitting
them duing emit_ib, emit_pipeline_sync and emit_vm_flush.

Note that it isn't necessary to emit these in both
emit_pipeline_sync() and emit_vm_flush() because
amdgpu_vm_flush() already calls these when calling
either of those functions.

Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
Signed-off-by: Timur Kristóf 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amd/display: Resize MST HDCP per-connector arrays to 32

2026-09-14T11:40:25+00:00

[ Upstream commit 261e0fe4e2c99f687114b64b10b98db964b475f4 ]

AMDGPU_DM_MAX_DISPLAY_INDEX is 31. It suggest a maximum number of
32 connectors. But the way it's used is like MAX_DISPLAY_COUNT.
Hence we're off by one with DRM core, which supports a max of 32
connectors.

Rename AMDGPU_DM_MAX_DISPLAY_INDEX to AMDGPU_DM_MAX_DISPLAY_COUNT
to match its actual use, and increase the size to 32 to match the
originally intended size.

Fixes: 82986fd631fa ("drm/amd/display: save restore hdcp state when display is unplugged from mst hub")
Assisted-by: Copilot:claude-opus-4.8
Reviewed-by: Alex Hung 
Signed-off-by: Harry Wentland 
Signed-off-by: Roman Li 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amdgpu/gfx6: Fixup emit_cntxcntl()

2026-09-14T11:40:25+00:00

[ Upstream commit 1edb323406aaf05739804d2faa2561f2d43bcd09 ]

Set bits on dword 2 like GFX7-8 except load_global_uconfig
which doesn't exist on GFX6.

Emit VS_PARTIAL_FLUSH before VGT_FLUSH like GFX7-8.

For reference see old PAL which explains the bit fields in
this register and that load_global_uconfig doesn't exist on GFX6
and also see gfx_v7_ring_emit_cntxcntl() for the GFX7 code
which this commit follows.

Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
Signed-off-by: Timur Kristóf 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amdgpu: read TRUNCATE_COORD_MODE on gfx12

2026-09-14T11:40:25+00:00

[ Upstream commit 4261cbc7b03f1f56e95aeaf1492b8690fa5a253e ]

TA_CNTL2.TRUNCATE_COORD_MODE selects whether texture coordinate
truncation is D3D9/GL/Vulkan conformant. gfx11 reads it and reports it to
userspace via AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, but gfx12 never
read it, so the flag was always reported as 0 and userspace fell back to
the non-conformant path.

Read it in gfx_v12_0_constants_init() like gfx11 does.

Fixes: 52cb80c12e8a ("drm/amdgpu: Add gfx v12_0 ip block support (v6)")
Signed-off-by: Qiang Yu 
Reviewed-by: Marek Olšák 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/gfx12: Program DB_RING_CONTROL

2026-09-14T11:40:25+00:00

[ Upstream commit 402ebe22b267783f3b05b714df224fad0223b278 ]

This is needed to allocate occlusion counters across
both gfx pipes. GFX 12 only has one gfx pipe, so no functional
change since the default value is 1.

Reviewed-by: Timur Kristóf 
Signed-off-by: Alex Deucher 
Stable-dep-of: 4261cbc7b03f ("drm/amdgpu: read TRUNCATE_COORD_MODE on gfx12")
Signed-off-by: Sasha Levin

drm/amd/display: remove duplicate link_dp_panel_replay.h include

2026-09-14T11:39:32+00:00

[ Upstream commit dcda83715716ac828454094ed9c6e17150a0092f ]

link_dp_irq_handler.c includes "link_dp_panel_replay.h" twice. Drop the
redundant second include; this is a non-functional cleanup flagged by
scripts/checkincludes.pl.

Fixes: 1e5cd4adfc54 ("drm/amd/display: move panel replay out from edp")
Signed-off-by: Anas Khan 
Reviewed-by: George Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new

2026-09-14T11:39:32+00:00

[ Upstream commit db9c882f83d3f3e08069f52d0d2ebf9d131c9ae4 ]

dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but
passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second
REG_UPDATE_2 slot.

The current behavior is harmless on DCN3.5 because both fields share the
same bit layout, but it is still incorrect and could break on future
hardware revisions.

Fixes: d36771a03412 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL")
Signed-off-by: Dyllan Kobal 
Reviewed-by: George Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin

drm/amd/display: Remove unused-but-set variable hubp from

2026-09-14T11:39:31+00:00

[ Upstream commit b736792e5bd4a62f24e8d1e310bf4a75bfbeaaaa ]

The final check of hubp for NULL covers all remaining lines of code, since
the value of hubp does not change until the end of the method.

This check is redundant because hubp1 is already dereferenced within the
macro.
If it were NULL, the program would have already failed to proceed.

Remove the left part of the expression with the logical "&&".

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: be1fb44389ca ("drm/amd/display: Check null pointers before used").
Signed-off-by: Gleb Markov 
Reviewed-by: George Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin