linux-stable.git/drivers/gpu/drm/amd/include/asic_reg, branch v4.8 Linux kernel stable tree drm/amdgpu: add new definition in bif header 2016-07-29T18:37:11+00:00 Huang Rui ray.huang@amd.com 2016-07-14T16:31:05+00:00 e595d7f03b48f5f311c9289c070a2a14636ad362 This patch adds new definition in bif header, and will be used on iceland HW powertune part. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This patch adds new definition in bif header, and will be used on
iceland HW powertune part.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: implement UVD VM mode for Stoney v2 2016-07-29T18:36:57+00:00 Christian König christian.koenig@amd.com 2016-06-23T10:11:46+00:00 0f30a397d9824cc81722d9912ae6ec9cec2b929b Starting with Stoney we support running UVD in VM mode as well. v2: rebased, only enable on Polaris for now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Starting with Stoney we support running UVD in VM mode as well.

v2: rebased, only enable on Polaris for now.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: add shared definitions for di/dt feature. 2016-07-07T19:06:22+00:00 Rex Zhu Rex.Zhu@amd.com 2016-06-08T04:52:16+00:00 9a88d22bb090f39e234bec9e4d416c8acdcdbb93 v1: delete some comflict definitions between polaris and fiji. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
v1: delete some comflict definitions between polaris and fiji.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: remove gfx8 registers that vary between asics 2016-07-07T19:06:21+00:00 Ken Wang Qingqing.Wang@amd.com 2016-07-01T05:54:23+00:00 a334bc7df010b5d427b6f37bc9db34759e372a2e those register mask definitions are different in polaris compare to former gfx 8 gpus, so remove them from misusing. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
those register mask definitions are different in polaris compare to
former gfx 8 gpus, so remove them from misusing.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx80: Add QUICK_PG bit to GFX header and use it. 2016-07-07T18:51:19+00:00 Tom St Denis tom.stdenis@amd.com 2016-06-03T18:31:46+00:00 78f73bf03c131c5428383aa34e273be80965dd06 Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3D 2016-05-05T00:25:02+00:00 Flora Cui Flora.Cui@amd.com 2015-11-05T04:42:59+00:00 d7120b8f227bd0aaa87f10861848faff47eed7af Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: add DCE 11.2 register headers 2016-05-05T00:23:19+00:00 Alex Deucher alexander.deucher@amd.com 2016-03-11T19:46:46+00:00 7edbb0d389ccad68a75a2dcdbeb682014f1ccffe Add register headers for DCE (Display and Composition Engine) 11.2. Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add register headers for DCE (Display and Composition Engine)
11.2.

Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: handle more than 10 UVD sessions (v2) 2016-05-05T00:20:23+00:00 Arindam Nath arindam.nath@amd.com 2016-04-12T11:46:15+00:00 c036554170fcc2238c32a7edd72c1b61b886428a Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Change History
--------------

v2:
- Make firmware version check correctly. Firmware
  versions >= 1.80 should all support 40 UVD
  instances.
- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
  variable.

v1:
- The firmware can handle upto 40 UVD sessions.

Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx7: add MTYPE definition 2016-03-17T17:15:43+00:00 Flora Cui flora.cui@amd.com 2015-10-12T02:12:03+00:00 b9c743b85dc378510ef0e5ebe3c2e4ac1495c410 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Update dce 8 headers for dal 2016-02-12T20:31:47+00:00 Harry Wentland harry.wentland@amd.com 2016-02-11T01:01:39+00:00 e7813d0cd8b6183fcd967843ab1f53e43e05423c Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>