linux-stable.git/drivers/gpu/drm/amd/include/asic_reg, branch v4.7 Linux kernel stable tree drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3D 2016-05-05T00:25:02+00:00 Flora Cui Flora.Cui@amd.com 2015-11-05T04:42:59+00:00 d7120b8f227bd0aaa87f10861848faff47eed7af Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: add DCE 11.2 register headers 2016-05-05T00:23:19+00:00 Alex Deucher alexander.deucher@amd.com 2016-03-11T19:46:46+00:00 7edbb0d389ccad68a75a2dcdbeb682014f1ccffe Add register headers for DCE (Display and Composition Engine) 11.2. Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add register headers for DCE (Display and Composition Engine)
11.2.

Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: handle more than 10 UVD sessions (v2) 2016-05-05T00:20:23+00:00 Arindam Nath arindam.nath@amd.com 2016-04-12T11:46:15+00:00 c036554170fcc2238c32a7edd72c1b61b886428a Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Change History
--------------

v2:
- Make firmware version check correctly. Firmware
  versions >= 1.80 should all support 40 UVD
  instances.
- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
  variable.

v1:
- The firmware can handle upto 40 UVD sessions.

Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx7: add MTYPE definition 2016-03-17T17:15:43+00:00 Flora Cui flora.cui@amd.com 2015-10-12T02:12:03+00:00 b9c743b85dc378510ef0e5ebe3c2e4ac1495c410 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Update dce 8 headers for dal 2016-02-12T20:31:47+00:00 Harry Wentland harry.wentland@amd.com 2016-02-11T01:01:39+00:00 e7813d0cd8b6183fcd967843ab1f53e43e05423c Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: add dce8 enum register header 2016-02-10T19:17:02+00:00 Alex Deucher alexander.deucher@amd.com 2016-01-27T16:09:50+00:00 f2802faa052994bf2a57094f0aad788c675ab519 This adds the DCE8 enum header. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This adds the DCE8 enum header.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.h 2015-12-21T21:42:12+00:00 yanyang1 young.yang@amd.com 2015-08-17T06:15:20+00:00 3a287055aed6634d57d57da1977f1df3c9206945 Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by new powerplay code for tonga and fiji. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> 
Add ixSWRST_COMMAND_1 in bif_5_0_d.h.  Required by
new powerplay code for tonga and fiji.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
drm/amd: add new gfx8 register definitions for EDC 2015-12-02T20:54:18+00:00 Alex Deucher alexander.deucher@amd.com 2015-11-24T22:42:02+00:00 aa5e24e5f8a83b19b1b19964f35562c7a42636e2 EDC is a RAS feature for on chip memory. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
EDC is a RAS feature for on chip memory.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add GFX 8.1 register headers 2015-10-28T20:49:03+00:00 Alex Deucher alexander.deucher@amd.com 2015-10-23T22:53:36+00:00 6bd53c4125e545a495fba63024d5522e33c600f5 Minor differences compared to GFX 8.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Minor differences compared to GFX 8.0

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add Fiji smu 7.1.3 headers (v2) 2015-08-17T20:50:25+00:00 David Zhang david1.zhang@amd.com 2015-07-08T11:13:25+00:00 d1c4dcfb76a0053ca7bcc90608b3699ac1e1b39d v2: agd5f: prepare for release Signed-off-by: David Zhang <david1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
v2: agd5f: prepare for release

Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>