linux-stable.git/drivers/gpu/drm/amd/include/asic_reg, branch linux-5.9.y Linux kernel stable tree drm/amdgpu: add VCN 3.0 AV1 registers 2020-09-18T03:05:57+00:00 Alex Deucher alexander.deucher@amd.com 2020-05-01T20:45:09+00:00 1b51916b9734acd609c4f552e582cdc59ac254d6 This adds the AV1 registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This adds the AV1 registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add the GC 10.3 VRS registers 2020-09-18T03:05:42+00:00 Alex Deucher alexander.deucher@amd.com 2020-05-01T20:42:56+00:00 5d5b71e8a0f2f5649991d651d005181dc087981c Add the VRS registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add the VRS registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm amdgpu: SI UVD registers 2020-07-01T05:59:24+00:00 Sonny Jiang sonny.jiang@amd.com 2020-06-10T20:02:21+00:00 2282b4186dee80c89906d0ee10295393582c3afd Add SI UVD registers files. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add SI UVD registers files.

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2) 2020-07-01T05:59:22+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-16T12:47:04+00:00 614c56111cc73f0a828634dcb2eecd2035c2104b Despite having different IP offsets the computed address of the register(s) are the same between gfx7..gfx10. This patch fixes the offset relative to the GC block on gfx10. (v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ... Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10.  This patch fixes the offset relative
to the GC block on gfx10.

(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers 2020-07-01T05:59:21+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-15T16:17:46+00:00 e3569fab49886123c81f18d675fb1719d73cf27d Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits 2020-07-01T05:59:19+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-11T11:54:13+00:00 8d7fb7a10a825bd2e2c0fde7979cd8774c332bea Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2) 2020-07-01T05:59:19+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-09T11:49:59+00:00 055e23e3d9ea1d680977f8e34f9678c17cb3cfc1 Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Requested for UMR support.

(v2): Also add reg/bits for gfx9 headers

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add dcn30 Headers (v2) 2020-06-03T17:51:56+00:00 Jerry (Fangzhi) Zuo Jerry.Zuo@amd.com 2020-03-03T21:50:25+00:00 241b2ec9317ec9fdf6e26d2025a4aadb5d74859a DCN 3.0 display controller registers v2: squash in updates from Bhawan. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
DCN 3.0 display controller registers

v2: squash in updates from Bhawan.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN3.0 register headers (v2) 2020-06-03T17:51:55+00:00 Leo Liu leo.liu@amd.com 2019-08-13T14:01:47+00:00 a5a2597771c3f53562cd200c67135835f945233c Sienna_Cichlid VCN headers v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Sienna_Cichlid VCN headers

v2: squash in updates (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add ATHUB 2.1 header files (v2) 2020-06-03T17:51:55+00:00 Yong Zhao Yong.Zhao@amd.com 2019-09-24T20:17:47+00:00 e54294d665f81da4005a1f616e4f040c0d696552 v2: squash in updates (Alex) Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
v2: squash in updates (Alex)

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>