linux-stable.git/drivers/gpu/drm/amd/include/asic_reg, branch linux-5.11.y Linux kernel stable tree drm/amdgpu: Add and use seperate reg headers for dcn302 2020-11-10T19:15:08+00:00 Bhawanpreet Lakha Bhawanpreet.Lakha@amd.com 2020-11-05T18:37:35+00:00 9713158cb2a918c3f6f5522eed23cdeb61f22e75 Currently we are using dcn3 reg headers for dcn302. The offsets are different between the two so they need seperate headers. Add dcn302 header files and use these instead of dcn3 header Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Currently we are using dcn3 reg headers for dcn302. The offsets are
different between the two so they need seperate headers.

Add dcn302 header files and use these instead of dcn3 header

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add GC 10.3 NOALLOC registers 2020-10-23T19:33:47+00:00 Alex Deucher alexander.deucher@amd.com 2020-05-01T20:41:41+00:00 d02792041c17c9f8e1f9ac1420dcfb7fe13b256c This adds the NOALLOC registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This adds the NOALLOC registers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add missing newline at eof 2020-10-15T16:20:12+00:00 Tom Rix trix@redhat.com 2020-10-14T21:18:06+00:00 234de272b76fedaf71ffe40f8e80212c8d32cc23 Representative checkpatch.pl warning WARNING: adding a line without newline at end of file 30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30: +#endif Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Representative checkpatch.pl warning

WARNING: adding a line without newline at end of file
 30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30:
+#endif

Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vangogh asic header files (v2) 2020-10-05T19:14:02+00:00 Huang Rui ray.huang@amd.com 2019-10-20T00:39:44+00:00 a5b2c10c05ef12739be9907cc35acd33dff09020 This patch is to add vangogh asic header files. v2: squash in updates Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This patch is to add vangogh asic header files.

v2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update athub interrupt harvesting handle 2020-09-22T21:37:38+00:00 Stanley.Yang Stanley.Yang@amd.com 2020-09-15T08:15:05+00:00 3f975d0f71d384825f47c3598d1d5358e40a57f5 GCEA/MMHUB EA error should not result to DF freeze, this is fixed in next generation, but for some reasons the GCEA/MMHUB EA error will result to DF freeze in previous generation, diver should avoid to indicate GCEA/MMHUB EA error as hw fatal error in kernel message by read GCEA/MMHUB err status registers. Changed from V1: make query_ras_error_status function more general make read mmhub er status register more friendly Changed from V2: move ras error status query function into do_recovery workqueue Changed from V3: remove useless code from V2, print GCEA error status instance number Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
GCEA/MMHUB EA error should not result to DF freeze, this is
fixed in next generation, but for some reasons the GCEA/MMHUB
EA error will result to DF freeze in previous generation,
diver should avoid to indicate GCEA/MMHUB EA error as hw fatal
error in kernel message by read GCEA/MMHUB err status registers.

Changed from V1:
    make query_ras_error_status function more general
    make read mmhub er status register more friendly

Changed from V2:
    move ras error status query function into do_recovery workqueue

Changed from V3:
    remove useless code from V2, print GCEA error status
    instance number

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN 3.0 AV1 registers 2020-09-17T22:01:46+00:00 Alex Deucher alexander.deucher@amd.com 2020-05-01T20:45:09+00:00 2f7c3686a6b26d86017180fab07751645b885f30 This adds the AV1 registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This adds the AV1 registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add the GC 10.3 VRS registers 2020-09-17T22:00:50+00:00 Alex Deucher alexander.deucher@amd.com 2020-05-01T20:42:56+00:00 7663edc13ed0a5390944e49038815ee0a8e7ae05 Add the VRS registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add the VRS registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700 2020-09-17T21:59:54+00:00 Tom St Denis tom.stdenis@amd.com 2020-09-16T16:17:04+00:00 b6c91dadaffee8bf253b0b5ac26a2638c388c6c6 This register was requested for umr debugging support. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This register was requested for umr debugging support.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling 2020-08-26T20:40:18+00:00 Alex Deucher alexander.deucher@amd.com 2020-08-18T23:24:03+00:00 f8646661f713fb7d33ebe404d418bd3fa55c383e Properly define this register using a relative offset rather than an absolute offset and use the proper SOC15 macros to access it. It's also DCN, not DCE, so remove it from the DCE12 header. No functional change. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it.  It's also DCN, not DCE, so remove it from the
DCE12 header.

No functional change.

Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: remove unintended executable mode 2020-08-24T16:23:02+00:00 Lukas Bulwahn lukas.bulwahn@gmail.com 2020-08-19T08:18:08+00:00 5049a0526988d575c777db20a52eba5efaadbd2a Besides the intended change, commit 4cc1178e166a ("drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhub") also set the source files mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode 644 to new mode 755. Commit 241b2ec9317e ("drm/amd/display: Add dcn30 Headers (v2)") added the four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e., mode 755. Set to the usual modes for source and headers files and clean up those mistakes. No functional change. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Besides the intended change, commit 4cc1178e166a ("drm/amdgpu: replace DRM
prefix with PCI device info for gfx/mmhub") also set the source files
mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode
644 to new mode 755.

Commit 241b2ec9317e ("drm/amd/display: Add dcn30 Headers (v2)") added the
four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e.,
mode 755.

Set to the usual modes for source and headers files and clean up those
mistakes. No functional change.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>