linux-stable.git/drivers/gpu/drm/amd/display/modules/inc, branch linux-6.3.y

drm/amd/display: Enable Freesync over PCon

2023-01-31T19:00:44+00:00

[why]
Enable Freesync over PCon on Linux environment.

[how]
Adding Freesync over PCon support in amdgpu_dm
- Read DPCD for Freesync over PCon capabilitiy
- Add whitelist for compatible branch devices

Reviewed-by: Chao-kai Wang 
Acked-by: Alex Hung 
Signed-off-by: Sung Joon Kim 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Enable AdaptiveSync in DC interface

2023-01-24T18:26:25+00:00

[why]
Start enabling AdaptiveSync feature on Linux environment.

[how]
Adding AdaptiveSync support in DC layer
- building AdaptiveSync info_packets
- adjusting the v_startup parameter

Reviewed-by: Harry Wentland 
Reviewed-by: Anthony Koo 
Acked-by: Alan Liu 
Signed-off-by: Sung Joon Kim 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Wrong colorimetry workaround

2022-10-27T18:45:14+00:00

[Why]
For FreeSync HDR, native color space flag in AMD VSIF(BT.709) should be
used when intepreting content and color space flag in VSC or AVI
infoFrame should be ignored. However, it turned out some userspace
application still use color flag in VSC or AVI infoFrame which is
incorrect.

[How]
Transfer function is used when building the VSC and AVI infoFrame. Set
colorimetry to BT.709 when all the following match:

1. Pixel format is YCbCr;
2. In FreeSync 2 HDR, color is COLOR_SPACE_2020_YCBCR;
3. Transfer function is TRANSFER_FUNC_GAMMA_22;

Tested-by: Mark Broadworth 
Reviewed-by: Krunoslav Kovac 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Ma Hanghong 
Signed-off-by: Alex Deucher

drm/amd/display: Add vrr_active_variable to dc_stream_update

2022-06-15T01:38:41+00:00

[WHY]
The display driver on some OSes need to track it in order to
perform memory clock switching decisions.

[HOW]
Propagate the vrr active state to dirty bit so that on mode set it
disables dynamic memory clock switching.

Acked-by: Alan Liu 
Signed-off-by: Harry VanZyllDeJong 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Firmware assisted MCLK switch and FS

2022-06-15T01:38:41+00:00

[WHY]
Memory clock switching has great potential for power savings.

[HOW]
The driver code was modified to notify the DMCUB firmware that it should
stretch the vertical blank of frames when a memory clock switch is about
to start so that no blackouts happen on the screen due to unavailability
of the frame buffer.
The driver logic to determine when such firmware assisted strategy can
be initiated is also implemented and consists on checking prerequisites
of the feature.

Acked-by: Alan Liu 
Signed-off-by: Felipe Clark 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add flip interval workaround

2022-04-05T14:29:47+00:00

[WHY]
Some games experience low FPS issues when FreeSync is on and VSync is
toggled to half refresh rate.

[HOW]
First create a function to determine workaround conditions, which is
when we detect 2 or more VSync interrupts between flips and a very short
VSync to flip interval. We do the workaround during VSync interrupts and
set the v_total_max and min to nominal. We also cleanup after we exit
the game.

Tested-by: Daniel Wheeler 
Reviewed-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Tom Chung 
Signed-off-by: Angus Wang 
Signed-off-by: Alex Deucher

drm/amd/display: Fix HDCP SEND AKI INIT error

2022-03-25T16:40:26+00:00

[why]
HDCP sends AKI INIT error in case of multiple display on dock

[how]
Add new checks and method to handle display adjustment
for multiple display cases

Reviewed-by: Wenjing Liu 
Acked-by: Alex Hung 
Signed-off-by: Ahmad Othman 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Update VSC HDR infoPacket on TF change

2022-01-25T23:00:35+00:00

[why]
OnSetSourceContentAttribute it does not trigger an update for the VSC
with TF change.

[how]
In this call, create a new VSC infoPacket based on the new config, and
allow DisplayTarget decide if an update and pursuant passive flip is
necessary

Tested-by: Daniel Wheeler 
Reviewed-by: Krunoslav Kovac 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Reza Amini 
Signed-off-by: Alex Deucher

drm/amd/display: unhard code link to phy idx mapping in dc link and clean up

2022-01-07T22:21:20+00:00

[why]
1. Current code hard codes link to PHY mapping in dc link level per asic
per revision.
This is not scalable. In long term the mapping will be obatined from
DMUB and store in dc resource.

2. Depending on DCN revision and endpoint type, the definition of
dio_output_idx dio_output_type and phy_idx are not  consistent. We need
to unify the meaning of these hardware indices across different system
configuration.

[how]
1. Temporarly move the hardcoded mapping to dc_resource level, which
should have full awareness of asic specific configuration and add a TODO
comment to move the mapping to DMUB.

2. populate dio_output_idx/phy_idx for all configuration, define
usb4_enabled bit instead of dio_output_type as an external enum.

Tested-by: Daniel Wheeler 
Reviewed-by: Eric Yang 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Wenjing Liu 
Signed-off-by: Alex Deucher

drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1

2021-10-28T18:26:14+00:00

[Why]
Created new fields that matches new B0 structs On DCN31 the mapping of
DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this
new mapping needed to be handled.

[How]
Mapped new structure based on new structs Added logic for mapping over
A0 and B0 boards Hooked all new structs together.

Reviewed-by: Wenjing Liu 
Acked-by: Agustin Gutierrez 
Tested-by: Daniel Wheeler 
Signed-off-by: Ahmad Othman 
Signed-off-by: Alex Deucher