linux-stable.git/drivers/gpu/drm/amd/display/dc/dce, branch v5.10

drm/amd/display: Fixed panic during seamless boot.

2020-10-26T21:10:27+00:00

[why]
get_pixel_clk_frequency_100hz is undefined in clock_source_funcs.

[how]
set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz"

Signed-off-by: David Galiffi 
Reviewed-by: Bhawanpreet Lakha 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Ensure all debug bits are passed to fw

2020-09-29T20:08:37+00:00

[Why]
Some debug bits are not being copied from driver to fw.

[How]
Copy debug bits properly.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Implement PSR wait for enable/disable

2020-09-22T16:28:49+00:00

[Why]
For DMUB implementation of PSR, the 'wait' parameter,
used to determine if driver should wait for PSR enable/disable,
is not implemented correctly.

[How]
Implement wait for PSR enable/disable.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alex Deucher

drm/amd/display: Bug in dce_is_panel_backlight_on()

2020-09-22T16:27:35+00:00

[Why]
dce_is_panel_backlight_on() will return wrong value if
LVTMA_BLON_OVRD is 0

[How]
When LVTMA_BLON_OVRD is 0, read
LVTMA_PWRSEQ_TARGET_STATE instead

Signed-off-by: Peikang Zhang 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alex Deucher

drm/amd/display: Fix incorrect backlight register offset for DCN

2020-09-22T16:27:10+00:00

[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: David Galiffi 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alex Deucher 
Cc:

drm/amd/display: Rename set_mst_bandwidth to align with DP spec

2020-09-15T21:52:41+00:00

[Why]
The function set_mst_bandwidth is poorly name since it isn't clear what
it does, and it also does not reflect any part of the allocation sequence
described in the DP spec.

[How]
Rename the function set_mst_bandwidth to set_throttled_vcp_size.

Signed-off-by: George Shen 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: fix potential integer overflow when shifting 32 bit variable bl_pwm

2020-08-18T22:22:43+00:00

The 32 bit unsigned integer bl_pwm is being shifted using 32 bit arithmetic
and then being assigned to a 64 bit unsigned integer.  There is a potential
for a 32 bit overflow so cast bl_pwm to enforce a 64 bit shift operation
to avoid this.

Addresses-Coverity: ("unintentional integer overflow")
Fixes: 3ba01817365c ("drm/amd/display: Move panel_cntl specific register from abm to panel_cntl.")
Signed-off-by: Colin Ian King 
Signed-off-by: Alex Deucher

drm/amd/display: Add read backlight interface

2020-08-17T18:08:12+00:00

[Why & How]
Add read backlight interface to get ABM data.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Fix incorrect backlight register offset for DCN

2020-08-10T21:26:52+00:00

[Why]
Typo in backlight refactor inctroduced wrong register offset.

[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV

Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr 
Reviewed-by: Ashley Thomas 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alex Deucher

drm/amd/display: Read VBIOS Golden Settings Tbl

2020-08-04T21:29:27+00:00

[Why]
For ver.4.4 and higher VBIOS contains default setting table.

{How]
Read Golden Settings Table from VBIOS, apply Aux tuning parameters.

Signed-off-by: Igor Kravchenko 
Reviewed-by: Aric Cyr 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher