linux-stable.git/drivers/gpu/drm/amd/display/dc/dce, branch master

drm/amd/display: use proper context for logging

2026-07-29T00:01:24+00:00

The same as the rest of the code, get_ss_info_from_atombios() uses
calc_pll_cs->ctx->logger for logging. But calc_pll_cs->ctx is
initialized only later in calc_pll_max_vco_construct(). Therefore, any
output using DC_LOG_SYNC() leads to a NULL pointer deference in
get_ss_info_from_atombios().

According to Sashiko, the very same problem exists in
dce112_get_pix_clk_dividers() and dcn3_get_pix_clk_dividers() too.

To avoid accessing the NULL context, use clk_src->base.ctx->logger
everywhere. That context in base is initialized earlier in
dce110_clk_src_construct() and dce112_clk_src_construct(). Before
get_ss_info_from_atombios() or Sashiko's get_pix_clk_dividers functions
above are actually called. This is done by redefining DC_LOGGER to
CTX->logger.

Before:
dce110_clk_src_construct() did:
 -> sets clk_src->base.ctx = ctx;
 -> ss_info_from_atombios_create()
   -> get_ss_info_from_atombios()   <- uses calc_pll_cs->ctx  # BOOM
 -> calc_pll_max_vco_construct()    <- sets calc_pll_cs->ctx

After:
dce110_clk_src_construct() does:
 -> sets clk_src->base.ctx = ctx;
 -> ss_info_from_atombios_create()
   -> get_ss_info_from_atombios()   <- uses clk_src->base.ctx

Closes: https://bugzilla.suse.com/show_bug.cgi?id=1271175
Closes: https://lore.kernel.org/all/a9ee54e6-2413-4156-9bde-d528ae3c63a3@kernel.org/
Fixes: 1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
Reviewed-by: Bhawanpreet Lakha 
Signed-off-by: Jiri Slaby (SUSE) 
Cc: Lakha, Bhawanpreet 
Cc: Harry Wentland 
Cc: Leo Li 
Cc: Rodrigo Siqueira 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Simona Vetter 
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Alex Deucher 
(cherry picked from commit 6f16fcbb0c46a87e3d9685407e906573d60104b0)
Cc: stable@vger.kernel.org

drm/amd/display: fix __udivdi3 link error

2026-07-17T21:39:36+00:00

When compiling the AMDGPU display driver for 32-bit architectures,
the linker reports undefined reference to `__udivdi3` in functions
get_dp_dto_frequency_100hz() and dcn401_get_dp_dto_frequency_100hz().

This is because the code uses 64-bit division (/) on 32-bit systems,
which GCC cannot handle directly and instead tries to call the missing
__udivdi3 helper function.

Replace the raw division with div_u64(), the kernel's standard 64-bit
division helper, to avoid the link error.

Signed-off-by: Linlin Yang 
Reported-by: k2ci 
Signed-off-by: Alex Deucher 
(cherry picked from commit 0421fc6ab3a8514e99156ff3c2cee13ee9af3fa7)
Cc: stable@vger.kernel.org

drm/amd/display: set MSA MISC1 bit 6 when using VSC SDP for DCE 11.x

2026-07-01T16:58:21+00:00

When BT.2020 colorimetry is selected, the driver sends information using
VSC SDP but does not set "ignore MSA colorimetry" bit on older GPUs with
DCE-based IPs. This causes certain sinks to prefer colorimetry
information in DP MSA, resulting in terrible color rendering ("dull"
colors) when HDR is enabled.

This commit wires up the MISC1 bit 6 for GPUs with DCE 11.x based IPs to
correctly configure sinks to ignore colorimetry information in MSA,
resolving the color rendering issue.

Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/4849
Assisted-by: oh-my-pi:GPT-5.5
Signed-off-by: Leorize 
Signed-off-by: Alex Deucher 
(cherry picked from commit 323a09e56c1d549ce47d4f110de77b0051b4a8bf)
Cc: stable@vger.kernel.org

drm/amd/display: Add support for FRL to DC core

2026-06-03T17:44:46+00:00

Here we add support for reading BIOS caps and tie FRL bits
into the rest of DC core.

Signed-off-by: Harry Wentland 
Reviewed-by: Fangzhi Zuo 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add no_native_i2c codepath

2026-06-03T17:43:29+00:00

[Why]
ASICs which do not have native DDC capability must use a different
codepath to access the AUX channel.

[How]
- BIOS cap NO_DDC_PIN is set to 1 for links which do not have the DDC pin.
- dp_connector_no_native_i2c in dc_config must also be set to true to
  use this codepath.

Reviewed-by: Harry Wentland 
Signed-off-by: Matthew Stewart 
Signed-off-by: Ray Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix DP_PIXEL_FORMAT fields & update clk_src for DCN4x

2026-06-03T17:39:58+00:00

[Why & How]
The enc1_stream_encoder_dp_get_pixel_format() function reads fields of the
DP_PIXEL_FORMAT register that are deprecated on DCN4x. This breaks seamless
boot because driver cannot properly determine the pixel format programmed by VBIOS.
The previous changed submitted for this issue incorrectly calculated the DP DTO
frequency because register access to DCN4x DP DTO registers was not working.

Create a new function that reads the correct fields.
Update clk_src structs to support register access for new DCN4x registers & fields.

Reviewed-by: Charlene Liu 
Signed-off-by: Ovidiu Bunea 
Signed-off-by: Ray Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: add missing CSC entries for BT.2020 for DCE IPs

2026-06-03T17:31:32+00:00

DCE-based hardware does not have the CSC matrices for BT.2020, which
causes the driver to fallback to the GPU built-in matrices. This does
not appear to cause any issues for RGB sinks, but causes major color
artifacts for YCbCr ones (e.g. black becomes green).

This commit adds the missing CSC matrices (taken from DC common) to DCE
CSC tables, resolving the issue.

Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/3358
Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5333
Assisted-by: oh-my-pi:GPT-5.5
Signed-off-by: Leorize 
Reviewed-by: Alex Hung 
Signed-off-by: Alex Deucher

drm/amd/display: Update get_pixel_clk_frequency() for DCN4x DCCG DP DTO

2026-06-03T17:31:08+00:00

[Why & How]
DCN4x ASICs have different DCCG logic for programming DP DTO. The current
get_pixel_clk_frequency_100hz() function does not account for this.

Rename the function to "get_dp_dto_frequency" to more accurately
reflect its intended behaviour. Create a new function that correctly
calculates the target pixel rate for DCN4.x DCCG design and use it.

Reviewed-by: Leo Chen 
Signed-off-by: Ovidiu Bunea 
Signed-off-by: Ray Wu 
Signed-off-by: Alex Deucher

drm/amd/display: Refactor dc_link_aux_transfer_raw

2026-05-11T20:10:41+00:00

[Why & How]
The logic for choosing between the dce_aux_transfer function variants is
moved into dce_aux.c rather than link_ddc.c.

The "dce_aux_transfer_with_retries" function now uses
dce_aux_transfer_raw in its implementation as the logic is equivalent.

Reviewed-by: Nevenko Stupar 
Reviewed-by: Gabe Teeger 
Signed-off-by: Matthew Stewart 
Signed-off-by: James Lin 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix type mismatches using guards and explicit casts

2026-05-05T13:56:52+00:00

[Why]
Address signed/unsigned comparison warnings across dc paths to keep
builds warning-clean and improve type safety at comparison boundaries.
Most warnings came from signed loop/index temporaries compared against
unsigned counters and table sizes, plus a smaller number of mixed
signed/unsigned clock, bandwidth, and geometry comparisons.

[How]
Aligned iterator and temporary variable types with the semantic type
of the compared bounds. Used unsigned indices for loops bounded by unsigned
counters and table sizes, while retaining signed types where values are
semantically signed or participate in arithmetic that may legitimately go
negative. Where mixed signed/unsigned comparisons are intentional, applied
explicit boundary casts or guarded comparisons instead of broad type
changes.

No functional behavior changes are intended; this is a warning-resolution
and type-alignment cleanup.

Reviewed-by: Dillon Varone 
Signed-off-by: Gaghik Khachatrian 
Signed-off-by: James Lin 
Signed-off-by: Alex Deucher