linux-stable.git/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c, branch v4.18.2 Linux kernel stable tree drm/amd/display: Convert 10kHz clks from PPLib into kHz for Vega 2018-07-12T14:48:57+00:00 Harry Wentland harry.wentland@amd.com 2018-07-12T14:23:21+00:00 d89d01f2232b90e8024ae07ff5ab213521875448 The driver is expecting clock frequency in kHz, while SMU returns the values in 10kHz, which causes the bandwidth validation to fail 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency only, which is only used by Vega. Make sure we multiply these values by 10 here, as we do for other ASICs as powerplay assigned them wrong. 4.19 has the proper fix in powerplay. v2: Add Fixes tag v3: Fixes -> Bugzilla, with simplified link Bugzilla: https://bugs.freedesktop.org/107082 Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
The driver is expecting clock frequency in kHz, while SMU returns
the values in 10kHz, which causes the bandwidth validation to fail

4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
only, which is only used by Vega. Make sure we multiply these values
by 10 here, as we do for other ASICs as powerplay assigned them
wrong. 4.19 has the proper fix in powerplay.

v2: Add Fixes tag
v3: Fixes -> Bugzilla, with simplified link

Bugzilla: https://bugs.freedesktop.org/107082

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/display: check if ppfuncs exists before using it 2018-05-30T17:38:05+00:00 Alex Deucher alexander.deucher@amd.com 2018-05-30T14:34:23+00:00 9dac0c3fb41056ae48b93e679c2a796c4dcfa8ed Fixes a crash on asics without powerplay yet (e.g., vega20). Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Fixes a crash on asics without powerplay yet (e.g., vega20).

Reviewed-by: Rex Zhu<rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix wrong latency assignment for VEGA clock levels 2018-05-29T18:16:48+00:00 Harry Wentland harry.wentland@amd.com 2018-05-29T13:59:13+00:00 10dd2b865393bb45526ca342fe69207341f89fd5 Also drop wrong 10kHz comment Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Also drop wrong 10kHz comment

Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency 2018-05-25T16:01:49+00:00 Harry Wentland harry.wentland@amd.com 2018-05-18T21:07:06+00:00 bfdec234047889f4f6af1ec45c7c502a4405b3fb This is required so we use the correct minimum clocks for Vega. Without this pplib will never be able to enter the lowest clock states. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This is required so we use the correct minimum clocks for Vega. Without
this pplib will never be able to enter the lowest clock states.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: add delay between panel pwr off to on. 2018-04-11T18:08:06+00:00 Charlene Liu charlene.liu@amd.com 2018-03-20T18:53:04+00:00 78d5d04d118d55b6c51ca787d5debb9ad1b8a391 As per eDP 1.4 spec, there must be at least 500ms delay between eDP power off and on. This change added time stamp when edp power off, which can be used to calculate duration time when edp power on. If duration less than 500ms, add a wait. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
As per eDP 1.4 spec, there must be at least 500ms delay
between eDP power off and on.
This change added time stamp when edp power off, which can
be used to calculate duration time when edp power on.
If duration less than 500ms, add a wait.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Implement dm_get_timestamp 2018-04-11T18:08:06+00:00 Harry Wentland harry.wentland@amd.com 2018-03-23T17:39:27+00:00 4c61af8afe855fcf65a09d47c8e330bb1fd1fb4a We use this to ensure we wait at least 500ms in between eDP disable/enable. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
We use this to ensure we wait at least 500ms in between eDP
disable/enable.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove unused dm_pp_ interfaces 2018-02-19T19:20:16+00:00 Harry Wentland harry.wentland@amd.com 2018-02-05T23:41:45+00:00 627c9a0a5002fed0ae818149e052301ec3abb93e Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: performance profiling instrumentation 2017-12-06T17:48:08+00:00 Tony Cheng tony.cheng@amd.com 2017-11-08T21:07:53+00:00 dce46c53208f90cf5a401b62b17bbe2bc629c069 Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: move functions to amd_pm_funcs table 2017-12-04T21:33:17+00:00 Rex Zhu Rex.Zhu@amd.com 2017-10-26T03:55:23+00:00 f685d714321daf660d9a9ecf9d4925c297223260 those functions are exported to DC Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
those functions are exported to DC

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: add performance trace macro to dc 2017-10-21T20:50:00+00:00 Dmytro Laktyushkin Dmytro.Laktyushkin@amd.com 2017-10-06T19:40:07+00:00 215a6f05bcc18ffcd953a8527639ea1f571f4d81 Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>