linux-stable.git/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c, branch v6.14

drm/amd/display: Disable PSR-SU on eDP panels

2025-02-25T17:26:51+00:00

[Why]
PSR-SU may cause some glitching randomly on several panels.

[How]
Temporarily disable the PSR-SU and fallback to PSR1 for
all eDP panels.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3388
Cc: Mario Limonciello 
Cc: Alex Deucher 
Reviewed-by: Sun peng Li 
Signed-off-by: Tom Chung 
Signed-off-by: Roman Li 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
(cherry picked from commit 6deeefb820d0efb0b36753622fb982d03b37b3ad)
Cc: stable@vger.kernel.org

drm/amd/display: Do not wait for PSR disable on vbl enable

2025-01-10T18:40:47+00:00

[Why]

Outside of a modeset/link configuration change, we should not have to
wait for the panel to exit PSR. Depending on the panel and it's state,
it may take multiple frames for it to exit PSR. Therefore, waiting in
all scenarios may cause perceived stuttering, especially in combination
with faster vblank shutdown.

[How]

PSR1 disable is hooked up to the vblank enable event, and vice versa. In
case of vblank enable, do not wait for panel to exit PSR, but still wait
in all other cases.

We also avoid a call to unnecessarily change power_opts on disable -
this ends up sending another command to dmcub fw.

When testing against IGT, some crc tests like kms_plane_alpha_blend and
amd_hotplug were failing due to CRC timeouts. This was found to be
caused by the early return before HW has fully exited PSR1. Fix this by
first making sure we grab a vblank reference, then waiting for panel to
exit PSR1, before programming hw for CRC generation.

Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for older ASICs")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3743
Reviewed-by: Tom Chung 
Signed-off-by: Leo Li 
Signed-off-by: Tom Chung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
(cherry picked from commit aa6713fa2046f4c09bf3013dd1420ae15603ca6f)
Cc: stable@vger.kernel.org

drm/amd/display: Fix possible overflow in integer multiplication

2024-07-01T20:06:53+00:00

[WHAT & HOW]
Integer multiplies integer may overflow in context that expects an
expression of unsigned/siged long long (64 bits). This can be fixed
by casting integer to unsigned/siged long long to force 64 bits results.

This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity.

Reviewed-by: Harry Wentland 
Signed-off-by: Jerry Zuo 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add periodic detection for IPS

2024-04-30T13:57:23+00:00

[Why]
HPD interrupt cannot be handled in IPS2 state.
So if there's a display topology change while system in IPS2
it can be missed.

[How]
Implement worker to check each 5 sec in IPS for HPD.

Reviewed-by: Hamza Mahfooz 
Acked-by: Wayne Lin 
Signed-off-by: Roman Li 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: fix IPX enablement

2024-03-27T05:33:11+00:00

We need to re-enable idle power optimizations after entering PSR. Since,
we get kicked out of idle power optimizations before entering PSR
(entering PSR requires us to write to DCN registers, which isn't allowed
while we are in IPS).

Fixes: a9b1a4f684b3 ("drm/amd/display: Add more checks for exiting idle in DC")
Tested-by: Mark Broadworth 
Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Hamza Mahfooz 
Signed-off-by: Alex Deucher

drm/amd/display: Fix function banner for amdgpu_dm_psr_disable_all()

2024-03-20T17:37:36+00:00

[WHY]
Incorrect function name in function banner.

[HOW]
Correct name and brief description.

Reviewed-by: Hersen Wu 
Reviewed-by: Aurabindo Pillai 
Acked-by: Alex Hung 
Signed-off-by: Roman Li 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add a new DC debug mask for PSR-SU

2023-12-19T19:47:15+00:00

Some issues have been raised that appear to be tied to PSR-SU.
To allow users to confirm they're tied to PSR-SU without turning off
PSR entirely introduce a new debug mask:

amdgpu.dcdebugmask=0x200

Reviewed-by: Harry Wentland 
Signed-off-by: Mario Limonciello 
Signed-off-by: Alex Deucher

drm/amd/display: Clean up warnings in amdgpu_dm _mst_types, _plane, _psr.c

2023-07-07T17:51:47+00:00

Fix the following warnings reported by checkpatch:

WARNING: Missing a blank line after declarations
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

Cc: Rodrigo Siqueira 
Cc: Aurabindo Pillai 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amd/display: Set minimum requirement for using PSR-SU on Rembrandt

2023-06-30T17:11:36+00:00

A number of parade TCONs are causing system hangs when utilized with
older DMUB firmware and PSR-SU. Some changes have been introduced into
DMUB firmware to add resilience against these failures.

Don't allow running PSR-SU unless on the newer firmware.

Cc: stable@vger.kernel.org
Cc: Sean Wang 
Cc: Marc Rossi 
Cc: Hamza Mahfooz 
Cc: Tsung-hua (Ryan) Lin 
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443
Signed-off-by: Mario Limonciello 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: Pass DSC slice height to PSR FW

2023-01-24T18:26:25+00:00

[Why]
When DSC is enabled, the PSRSU seletive update region
must be multiple number of DSC slice height number.
The original solution is to overwrite the SU Y granularity
by DSC slice height in DAL driver. However, the size
of the SU Y granularity variable only has 8 bytes
and the DSC slice height may over the 8 bytes size.

[How]
Instead of overwriting the SU Y granularity value,
add a new DSC slice height pararmeter and pass it
to DMUB PSRSU FW. The PSRSU FW will refer to the
DSC slice height value and extend the SU region.

Reviewed-by: Dennis Chan 
Reviewed-by: ChunTao Tso 
Acked-by: Alan Liu 
Signed-off-by: Robin Chen 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher