linux-stable.git/drivers/gpu/drm/amd/amdgpu/soc15.h, branch linux-5.5.y Linux kernel stable tree drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10 2019-11-22T19:55:19+00:00 changzhu Changfeng.Zhu@amd.com 2019-11-19T03:13:29+00:00 f920d1bb9c4e77efb08c41d70b6d442f46fd8902 It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation. After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 
It may lose gpuvm invalidate acknowldege state across power-gating off
cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
before invalidation and semaphore release after invalidation.

After adding semaphore acquire before invalidation, the semaphore
register become read-only if another process try to acquire semaphore.
Then it will not be able to release this semaphore. Then it may cause
deadlock problem. If this deadlock problem happens, it needs a semaphore
firmware fix.

Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: change to query the actual EDC counter 2019-10-15T19:49:44+00:00 Dennis Li Dennis.Li@amd.com 2019-10-12T05:00:22+00:00 13ba03442a2621952916de9036eb29f07c5ec891 For the potential request in the future, change to query the actual EDC counter. Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <hawking.zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
For the potential request in the future, change to
query the actual EDC counter.

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: dynamically initialize IP offset for Arcturus 2019-07-18T19:18:02+00:00 Le Ma le.ma@amd.com 2019-07-09T14:21:53+00:00 e78705ec5a7f607a3340c71a104b0d1c327958a4 Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add support for the IP offsets on Arcturus.

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10 2019-06-21T23:59:23+00:00 Hawking Zhang Hawking.Zhang@amd.com 2019-05-10T16:05:13+00:00 44f1bb1fed2596330ab55192ddb280865ebc79d2 Move to the header file. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Move to the header file.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fixed missing to clear some EDC count 2019-06-11T16:57:38+00:00 James Zhu James.Zhu@amd.com 2019-06-04T16:49:02+00:00 052af915d826b33588749566145c9417fcfc7246 EDC counts are related to instance and se. They are not the same for different type of EDC. EDC clearing are changed to base on individual EDC's instance and SE number. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
EDC counts are related to instance and se. They are not the same
for different type of EDC. EDC clearing are changed to base on
individual EDC's instance and SE number.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled 2019-05-24T17:20:50+00:00 James Zhu James.Zhu@amd.com 2019-04-05T19:31:47+00:00 5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Doorbell layout for vega20 and future asic 2018-11-28T20:55:32+00:00 Oak Zeng ozeng@amd.com 2018-11-19T21:59:53+00:00 c93aa77586c2ffe328cca32b40fc988bde8318b2 This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This introduces new doorbell layout for vega20 and future asics

v2: Use enum definition instead of hardcoded value

Signed-off-by: Oak Zeng <ozeng@amd.com>
Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Vega10 doorbell index initialization 2018-11-28T20:55:31+00:00 Oak Zeng ozeng@amd.com 2018-11-19T15:25:37+00:00 062f380725376efab279956b5441071684c2a7ff v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
v2: Use enum definition instead of hardcoded value
v3: Remove unused enum definition

Signed-off-by: Oak Zeng <ozeng@amd.com>
Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add nbio 7.4 support for vega20 (v3) 2018-08-27T16:10:23+00:00 Feifei Xu Feifei.Xu@amd.com 2018-03-23T19:44:28+00:00 fe3c948918e7e3d18eed85571d32a2f7c4b63a84 Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20. v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Some register offset in nbio v7.4 are different with v7.0.
We need a seperate nbio_v7_4.c for vega20.

v2: fix doorbell range for sdma (Alex)
v3: squash in static fix (kbuild test robot)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: dynamic initialize ip offset for vega20 2018-05-17T15:13:17+00:00 Feifei Xu Feifei.Xu@amd.com 2018-03-23T19:42:28+00:00 8ee273e516a096ee00b3be7cc15c8924aa3b1ef1 Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Vega20 need a seperate vega20_reg_init.c due to ip base
offset difference.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>