linux-stable.git/drivers/gpu/drm/amd/amdgpu/nv.c, branch linux-5.12.y Linux kernel stable tree drm/amdgpu: fix the hang caused by PCIe link width switch 2021-07-19T08:01:15+00:00 Evan Quan evan.quan@amd.com 2021-05-25T06:36:29+00:00 72270f52b87f75df5e83cf8cdc891d8059da1882 commit adcf949e664a8b04df2fb8aa916892e58561653c upstream. SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit adcf949e664a8b04df2fb8aa916892e58561653c upstream.

SMU had set all the necessary fields for a link width switch
but the width switch wasn't occurring because the link was idle
in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width
switches to also be initiated while in L1 instead of waiting until
the link is back in L0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu: fix NAK-G generation during PCI-e link width switch 2021-07-19T08:01:14+00:00 Evan Quan evan.quan@amd.com 2021-05-25T04:08:53+00:00 03cbd6eade56ff358ae443d6b45ffe35d4871057 commit 5a5da8ae9546031e43efd4fa5aa8baa481e83dfb upstream. A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit 5a5da8ae9546031e43efd4fa5aa8baa481e83dfb upstream.

A lot of NAK-G being generated when link widht switching is happening.
WA for this issue is to program the SPC to 4 symbols per clock during
bootup when the native PCIE width is x4.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu:disable VCN for Navi12 SKU 2021-03-04T03:48:33+00:00 Asher.Song Asher.Song@amd.com 2021-02-24T10:41:34+00:00 0c61ac8134ffc851681ce5d4bd60d97c3d5aed27 Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Asher.Song <Asher.Song@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 
Navi12 0x7360/C7 SKU has no video support, so remove it.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Asher.Song <Asher.Song@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu/nv: add PCI reset support 2021-02-09T20:30:01+00:00 Alex Deucher alexander.deucher@amd.com 2021-02-04T16:24:00+00:00 f172865a3632b85f29c2af9b044f4dd51581740f Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Use generic PCI reset for GPU reset if the user specifies
PCI reset as the reset mechanism.  This should in general
only be used for validation.

Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support rom clockgating related function for NV family 2021-02-09T20:28:36+00:00 Likun Gao Likun.Gao@amd.com 2021-02-03T10:45:42+00:00 1001f2a1f33dfe88bc7581d0177d01e9d299999c Add functions to support enable/disable rom clock gating and get rom clock gating status. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add functions to support enable/disable rom clock gating and get rom
clock gating status.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch to use smuio callbacks for NV family 2021-02-09T20:28:27+00:00 Likun Gao Likun.Gao@amd.com 2021-02-03T10:23:49+00:00 0bf7f2dcb9a65dcc9efb47e3a393108499d6a110 Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Switch to smuio callbacks: use smuio v11_0_6 callbacks for
Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the
other NV family ASIC.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support ASPM for some specific ASIC 2021-02-09T20:28:04+00:00 Likun Gao Likun.Gao@amd.com 2021-02-01T06:44:09+00:00 e1edaeafeb667688125ef1c4e2a098d2c798fc24 Support to program ASPM and LTR for Sienna Cichlid and forward ASIC. Disable ASPM for Sienna Cichlid and forward ASIC by default. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC.
Disable ASPM for Sienna Cichlid and forward ASIC by default.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: disable gpu reset on Vangogh for now 2021-01-28T19:58:10+00:00 Alex Deucher alexander.deucher@amd.com 2021-01-27T02:57:00+00:00 33cf440d594bfbf81fc20604957bc64f02d0b560 Until the issues in the SMU firmware are fixed. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> 
Until the issues in the SMU firmware are fixed.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
drm/amdgpu: fix mode2 reset sequence for vangogh 2021-01-14T04:47:58+00:00 Alex Deucher alexdeucher@gmail.com 2020-11-25T16:21:31+00:00 b913ec628ce2e701ba5a7d5f060f4d62d7a2ce06 We need to save and restore PCI config space. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> 
We need to save and restore PCI config space.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
drm/amdgpu/nv: add mode2 reset handling 2021-01-14T04:47:54+00:00 Alex Deucher alexdeucher@gmail.com 2020-11-25T16:21:30+00:00 1608635534fb8cc42e94d19d52789d9448f02536 Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> 
Vangogh will use mode2 reset, so plumb it through the nv
soc driver.

Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>