linux-stable.git/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h, branch v5.3 Linux kernel stable tree drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands 2019-08-02T15:36:34+00:00 Thong Thai thong.thai@amd.com 2019-07-25T15:21:58+00:00 af655cc5aae800f30cd71c5d72d36bd3ecb1e7df Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/VCN: implement indirect DPG SRAM mode 2019-06-21T23:59:33+00:00 Leo Liu leo.liu@amd.com 2019-05-27T14:46:25+00:00 dc8ae677c2a03891149a743fe50931bae4c506c5 SRAM will be programmed by PSP Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
SRAM will be programmed by PSP

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/VCN: add buffer for indirect SRAM usage 2019-06-21T23:59:33+00:00 Leo Liu leo.liu@amd.com 2019-05-24T18:07:41+00:00 a77b9fdf9aca3d9d8955487e95cd1e884b45fe1a This will be used later for indirect SRAM mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This will be used later for indirect SRAM mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/VCN2.0: add direct SRAM read and write 2019-06-21T23:59:32+00:00 Leo Liu leo.liu@amd.com 2019-05-24T16:19:00+00:00 19c663fc7799035f39f9833a2e3d82a2ed27b1e5 This will be the basic and used for DPG mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This will be the basic and used for DPG mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/VCN2.0: remove powergating for UVDW tile 2019-06-21T23:59:28+00:00 Leo Liu leo.liu@amd.com 2019-04-30T14:15:38+00:00 863dd269fa413ab8366cc42c8c2baade6f96de6e No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
No UVDW tile any more from VCN2.0, so mark out related fields.

It fixes error:
"[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa"

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add initial VCN2.0 support (v2) 2019-06-21T23:58:22+00:00 Leo Liu leo.liu@amd.com 2018-10-15T15:38:59+00:00 1b61de45dfaff00b627e47349a019658e39268b9 VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
VCN (Video Core Next) is the video encode/decode block.

Porting over the same functions from VCN1.0

v2: squash in updates (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add JPEG2.0 decode ring test 2019-06-21T23:58:22+00:00 Leo Liu leo.liu@amd.com 2018-12-03T16:42:28+00:00 9085914a5af4b3078a0289c4d67ee7cbc45dac99 Use register from JPEG tile, the UVD tile reg won't work for JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Use register from JPEG tile, the UVD tile reg won't work for JPEG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN2.0 decode ib test 2019-06-21T23:58:22+00:00 Leo Liu leo.liu@amd.com 2018-10-15T19:41:36+00:00 60a2309ec465aab22910ddce8e45aaa624f87f5d Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add internal register offset for registers involving in ib tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN2.0 decode ring test 2019-06-21T23:58:22+00:00 Leo Liu leo.liu@amd.com 2018-10-17T18:33:48+00:00 45a1a48b5c310700d338105df5883e8f8ab1f994 Add internal register offset for registers involving in ring tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add internal register offset for registers involving in ring tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: make VCN DPG pause mode detached from general VCN 2019-05-24T17:20:52+00:00 Leo Liu leo.liu@amd.com 2019-05-13T16:41:54+00:00 9dc7b02a3ccc78ca59fc20f466a166ca7e30d9e8 It should be attached to VCN 1.0 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
It should be attached to VCN 1.0

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>