linux-stable.git/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c, branch linux-5.17.y

Merge tag 'amd-drm-next-5.17-2021-12-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

2021-12-23T01:55:28+00:00

amdgpu:
- Add some display debugfs entries
- RAS fixes
- SR-IOV fixes
- W=1 fixes
- Documentation fixes
- IH timestamp fix
- Misc power fixes
- IP discovery fixes
- Large driver documentation updates
- Multi-GPU memory use reductions
- Misc display fixes and cleanups
- Add new SMU debug option

amdkfd:
- SVM fixes

radeon:
- Fix typo in comment

From: Alex Deucher 
Link: https://patchwork.freedesktop.org/patch/msgid/20211216202731.5900-1-alexander.deucher@amd.com

drm/amdgpu: fix incorrect VCN revision in SRIOV

2021-12-13T21:33:15+00:00

Guest OS will setup VCN instance 1 which is disabled as an enabled instance and
execute initialization work on it, but this causes VCN ib ring test failure
on the disabled VCN instance during modprobe:

amdgpu 0000:00:08.0: amdgpu: ring vcn_enc_1.0 uses VM inv eng 5 on hub 1
amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_dec_0 (-110).
amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_enc_0.0 (-110).
[drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110).

v2: drop amdgpu_discovery_get_vcn_version and rename sriov_config to
vcn_config
v3: modify VCN's revision in SR-IOV and bare-metal

Fixes: baf3f8f3740625 ("drm/amdgpu: handle SRIOV VCN revision parsing")
Signed-off-by: Leslie Shi 
Reviewed-by: Lijo Lazar 
Reviewed-by: Guchun Chen 
Signed-off-by: Alex Deucher

drm/amdgpu: handle SRIOV VCN revision parsing

2021-12-02T17:43:25+00:00

For SR-IOV, the IP discovery revision number encodes
additional information.  Handle that case here.

v2: drop additional IP versions

Reviewed-by: Guchun Chen 
Acked-by: Christian König 
Signed-off-by: Alex Deucher

drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID

2021-12-01T21:58:11+00:00

[WHY]
for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature),
which will be mismatched with original vcn0 revision

[HOW]
add new version check for vcn0 disabled revision(3, 0, 192), typically modified under
sriov mode

Signed-off-by: Jane Jian 
Reviewed-by: Guchun Chen 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID

2021-12-01T21:02:04+00:00

[WHY]
for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature),
which will be mismatched with original vcn0 revision

[HOW]
add new version check for vcn0 disabled revision(3, 0, 192), typically modified under
sriov mode

Signed-off-by: Jane Jian 
Reviewed-by: Guchun Chen 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64)

2021-11-10T17:03:41+00:00

Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking")
Signed-off-by: Flora Cui 
Signed-off-by: Guchun Chen 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: Consolidate VCN firmware setup code

2021-10-22T03:38:46+00:00

Roughly the same code was present in all VCN versions.
Consolidate it into a single function.

v2: use AMDGPU_UCODE_ID_VCN + i, check if num_inst >= 2

Signed-off-by: Alex Deucher 
Reviewed-by: Leo Liu 
Reviewed-by: James Zhu

drm/amdgpu: use adev_to_drm for consistency when accessing drm_device

2021-10-08T17:22:13+00:00

adev_to_drm is used everywhere, so improve recent changes
when accessing drm_device pointer from amdgpu_device.

Signed-off-by: Guchun Chen 
Acked-by: Christian König 
Signed-off-by: Alex Deucher

drm/amdgpu: convert IP version array to include instances

2021-10-04T19:23:01+00:00

Allow us to query instances versions more cleanly.

Instancing support is not consistent unfortunately. SDMA is a
good example.  Sienna cichlid has 4 total SDMA instances, each
enumerated separately (HWIDs 42, 43, 68, 69).  Arcturus has 8
total SDMA instances, but they are enumerated as multiple
instances of the same HWIDs (4x HWID 42, 4x HWID 43).  UMC
is another example.  On most chips there are multiple
instances with the same HWID.  This allows us to support both
forms.

v2: rebase
v3: clarify instancing support

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher

drm/amdgpu/amdgpu_vcn: convert to IP version checking

2021-10-04T19:23:00+00:00

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: squash in fix for navy flounder and sienna cichlid

Acked-by: Christian König 
Signed-off-by: Alex Deucher