linux-stable.git/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c, branch linux-5.14.y Linux kernel stable tree drm/amdgpu: correct psp ucode arrary start address 2021-06-15T21:25:42+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-06-11T16:51:22+00:00 ed4454c3844b06f00b89102cf3fba40fc73139bd For ASICs that need to load sys_drv_aux and sos_aux, the sys_start_addr is not the start address of psp ucode array because the sys_drv_aux and sos_aux actaully located at the end of the ucode array, instead, the psp ucode arrary start address should be sos_hdr + sos_hdr_offset. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
For ASICs that need to load sys_drv_aux and sos_aux,
the sys_start_addr is not the start address of psp
ucode array because the sys_drv_aux and sos_aux actaully
located at the end of the ucode array, instead, the
psp ucode arrary start address should be sos_hdr +
sos_hdr_offset.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: disable DRAM memory training when GECC is enabled 2021-06-11T20:06:21+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-06-07T05:22:08+00:00 3a07101b0405c6137babd5f50ca6bdf2696d91c9 GECC and G6 mem training are mutually exclusive functionalities. VBIOS/PSP will set the flag (BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in runtime database to indicate whether dram memory training need to be disabled or not. For Navi1x families, two stage mem training is always enabled. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
GECC and G6 mem training are mutually exclusive
functionalities. VBIOS/PSP will set the flag
(BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) in
runtime database to indicate whether dram memory
training need to be disabled or not.

For Navi1x families, two stage mem training is always
enabled.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: cache psp runtime boot_cfg_bitmask in sw_int 2021-06-11T20:06:15+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-06-07T03:02:13+00:00 8e6e054da6c72210966c82f7d3e7a3d014bd0b39 PSP runtime boot_cfg_bitmask carries various psp bl feature bit mask that can be used by driver. Cache it in sw_init for further usage. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
PSP runtime boot_cfg_bitmask carries various psp bl
feature bit mask that can be used by driver. Cache
it in sw_init for further usage.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add helper function to query psp runtime db entry (v2) 2021-06-11T20:06:03+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-06-07T12:31:30+00:00 3d689ae4a9741d60352e947f614079e2d3df8b44 PSP will dump various boot up information into a portion of local frame buffer, called runtime database. The helper function is used for driver to query those shared information. v2: init ret and check !ret to exit loop as soon as found the entry Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
PSP will dump various boot up information into a
portion of local frame buffer, called runtime database.
The helper function is used for driver to query those
shared information.

v2: init ret and check !ret to exit loop as soon as
found the entry

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable dynamic GECC support (v2) 2021-06-11T20:05:51+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-06-07T12:17:02+00:00 6246a416eb870bb9998eb40fcfa116a0fd9bf7e0 Dynamic GECC allows user to specify GECC enablement status, which will take effect in next boot cycle. v2: initialize boot_cfg to 0xFF Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Dynamic GECC allows user to specify GECC enablement
status, which will take effect in next boot cycle.

v2: initialize boot_cfg to 0xFF

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add helper function to query gecc status in boot config 2021-06-11T20:05:46+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-05-25T15:57:14+00:00 c6642234919c1cc11d2097c0868085ee19912477 Query GECC enablement status in boot config Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Query GECC enablement status in boot config

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: allow different boot configs 2021-06-11T20:05:41+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-05-25T13:20:44+00:00 55188d64edd72a33bc8fd0e42703140ce8e80bb0 More boot configs need to be supported via BOOTCFG_CMD_SET Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
More boot configs need to be supported via
BOOTCFG_CMD_SET

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pm: drop the incomplete fix for Navi14 runpm issue 2021-06-11T20:01:24+00:00 Evan Quan evan.quan@amd.com 2021-05-25T03:05:32+00:00 5f0f1727c46ef551acf87c2ce3c616dc8798a15d As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.quan@amd.com/ Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to
be incomplete. Another fix(see link below) has been sent out.
Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.quan@amd.com/

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Added support for loading auxiliary PSP FW 2021-06-10T15:44:24+00:00 John Clements john.clements@amd.com 2021-06-09T05:34:38+00:00 2a9a151fe852c1da39914221dd25238d60b09a93 In the case with xgmi connected to cpu load alternate psp fw Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
In the case with xgmi connected to cpu load alternate psp fw

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Updated fw header structure source 2021-06-10T15:44:24+00:00 John Clements john.clements@amd.com 2021-06-09T05:33:56+00:00 79a0f4415c9c6b63c14e90d8810f9e0636df34f6 synchronized fw header with latest source Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
synchronized fw header with latest source

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>