linux-stable.git/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v4.7.3

drm/amdgpu: fix lru size grouping v2

2016-09-07T06:34:50+00:00

commit 5661538749511d4c2f7d33e1e179f10c545b24d5 upstream.

Adding a BO can make it the insertion point for larger sizes as well.

v2: add a comment about the guard structure.

Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: Change GART offset to 64-bit

2016-09-07T06:34:50+00:00

commit cab0b8d50e9bbef62c04067072c953433a87a9ff upstream.

The GART aperture size can be bigger than 4GB. Therefore the offset
used in amdgpu_gart_bind and amdgpu_gart_unbind must be 64-bit.

Reviewed-by: Christian König 
Signed-off-by: Felix Kuehling 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman

Revert "drm/amdgpu: add pipeline sync while vmid switch in same ctx"

2016-06-13T22:59:17+00:00

This reverts commit 2ba272d7bde27e1db2cf1c6cee49b01b7ea08989.

The issue fixed by this patch is specific to compute rings and the
previous patch was enough.  Additionally, this patch as been traced
to strange behavior on some CZ systems so we might as well drop it.

amdgpu: fix asic initialization for virtualized environments (v2)

2016-06-13T19:25:20+00:00

When executing in a PCI passthrough based virtuzliation environemnt, the
hypervisor will usually attempt to send a PCIe bus reset signal to the
ASIC when the VM reboots. In this scenario, the card is not correctly
initialized, but we still consider it to be posted. Therefore, in a
passthrough based environemnt we should always post the card to guarantee
it is in a good state for driver initialization.

However, if we are operating in SR-IOV mode it is up to the GIM driver
to manage the asic state, therefore we should not post the card (and
shouldn't be able to do it either).

v2: add missing semi-colon

Reviewed-by: Christian König 
Signed-off-by: Andres Rodriguez 
Signed-off-by: Alex Deucher

drm/amdgpu: add pipeline sync while vmid switch in same ctx

2016-06-09T14:49:01+00:00

Since vmid-mgr supports vmid sharing in one vm, the same ctx could
get different vmids for two emits without vm flush, vm_flush could
be done in another ring.

Signed-off-by: Chunming Zhou 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: create fence slab once when amdgpu module init.

2016-05-13T18:30:22+00:00

This avoids problems with multiple GPUs.  For example,
if the first GPU failed before amdgpu_fence_init() was
called, amdgpu_fence_slab_ref is still 0 and it will
get decremented in amdgpu_fence_driver_fini().  This
will lead to a crash during init of the second GPU since
amdgpu_fence_slab_ref is not 0.

v2: add functions for init/exit instead of
    moving the variables into the driver.

Signed-off-by: Rex Zhu 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher

drm/amdgpu: fix and cleanup user fence handling v2

2016-05-11T17:30:32+00:00

We leaked the BO in the error pass, additional to that we only have
one user fence for all IBs in a job.

v2: remove white space changes

Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: move VM fields into job

2016-05-11T17:30:31+00:00

They are the same for all IBs.

Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: move the context from the IBs into the job

2016-05-11T17:30:31+00:00

We only have one context for all IBs.

Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amdgpu: move context switch handling into common code v2

2016-05-11T17:30:30+00:00

It was a source of bugs to repeat that in each IP version.

v2: rename parameter

Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher