<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/drivers/fpga, branch v6.0.7</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>fpga: prevent integer overflow in dfl_feature_ioctl_set_irq()</title>
<updated>2022-10-21T10:38:42+00:00</updated>
<author>
<name>Dan Carpenter</name>
<email>dan.carpenter@oracle.com</email>
</author>
<published>2022-09-01T05:18:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=940253af8b3865b76de8d1b46bcd4a700104852e'/>
<id>940253af8b3865b76de8d1b46bcd4a700104852e</id>
<content type='text'>
[ Upstream commit 939bc5453b8cbdde9f1e5110ce8309aedb1b501a ]

The "hdr.count * sizeof(s32)" multiplication can overflow on 32 bit
systems leading to memory corruption.  Use array_size() to fix that.

Fixes: 322b598be4d9 ("fpga: dfl: introduce interrupt trigger setting API")
Signed-off-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/YxBAtYCM38dM7yzI@kili
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[ Upstream commit 939bc5453b8cbdde9f1e5110ce8309aedb1b501a ]

The "hdr.count * sizeof(s32)" multiplication can overflow on 32 bit
systems leading to memory corruption.  Use array_size() to fix that.

Fixes: 322b598be4d9 ("fpga: dfl: introduce interrupt trigger setting API")
Signed-off-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/YxBAtYCM38dM7yzI@kili
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: dfl-pci: Add IDs for Intel N6000, N6001 and C6100 cards</title>
<updated>2022-10-21T10:38:42+00:00</updated>
<author>
<name>Matthew Gerlach</name>
<email>matthew.gerlach@linux.intel.com</email>
</author>
<published>2022-07-19T14:56:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=322f51f2091fb916a558392152fecbd15a873bfc'/>
<id>322f51f2091fb916a558392152fecbd15a873bfc</id>
<content type='text'>
[ Upstream commit 65f5c01033ab85f8d385d65c4b51fe31459da603 ]

Add pci_dev_table entries supporting the Intel N6000, N6001
and C6100 cards to the dfl-pci driver.

Signed-off-by: Matthew Gerlach &lt;matthew.gerlach@linux.intel.com&gt;
Signed-off-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Tested-by: Marco Pagani &lt;marpagan@redhat.com&gt;
Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Acked-by: Wu Hao &lt;hao.wu@intel.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220719145644.242481-1-matthew.gerlach@linux.intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[ Upstream commit 65f5c01033ab85f8d385d65c4b51fe31459da603 ]

Add pci_dev_table entries supporting the Intel N6000, N6001
and C6100 cards to the dfl-pci driver.

Signed-off-by: Matthew Gerlach &lt;matthew.gerlach@linux.intel.com&gt;
Signed-off-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Tested-by: Marco Pagani &lt;marpagan@redhat.com&gt;
Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Acked-by: Wu Hao &lt;hao.wu@intel.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220719145644.242481-1-matthew.gerlach@linux.intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: m10bmc-sec: Fix possible memory leak of flash_buf</title>
<updated>2022-09-19T04:58:19+00:00</updated>
<author>
<name>Russ Weight</name>
<email>russell.h.weight@intel.com</email>
</author>
<published>2022-09-16T23:52:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=468c9d928a8f38fdfaa61b05e81473cc7c8a6461'/>
<id>468c9d928a8f38fdfaa61b05e81473cc7c8a6461</id>
<content type='text'>
There is an error check following the allocation of flash_buf that returns
without freeing flash_buf. It makes more sense to do the error check
before the allocation and the reordering eliminates the memory leak.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Reported-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Fixes: 154afa5c31cd ("fpga: m10bmc-sec: expose max10 flash update count")
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Link: https://lore.kernel.org/r/20220916235205.106873-1-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is an error check following the allocation of flash_buf that returns
without freeing flash_buf. It makes more sense to do the error check
before the allocation and the reordering eliminates the memory leak.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Reported-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Fixes: 154afa5c31cd ("fpga: m10bmc-sec: expose max10 flash update count")
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Link: https://lore.kernel.org/r/20220916235205.106873-1-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: fpga-mgr: Fix spelling mistake "bitsream" -&gt; "bitstream"</title>
<updated>2022-06-29T07:18:18+00:00</updated>
<author>
<name>Colin Ian King</name>
<email>colin.i.king@gmail.com</email>
</author>
<published>2022-06-24T08:14:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ee794221a6f66d054beb1cbc151d8de4083e634e'/>
<id>ee794221a6f66d054beb1cbc151d8de4083e634e</id>
<content type='text'>
There is an spelling mistake in a dev_err message. Fix it.

Fixes: 3cc624beba63 ("fpga: fpga-mgr: support bitstream offset in image buffer")
Signed-off-by: Colin Ian King &lt;colin.i.king@gmail.com&gt;
Link: https://lore.kernel.org/r/20220624081409.14760-1-colin.i.king@gmail.com
[yilun.xu@intel.com: add the Fixes tag]
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is an spelling mistake in a dev_err message. Fix it.

Fixes: 3cc624beba63 ("fpga: fpga-mgr: support bitstream offset in image buffer")
Signed-off-by: Colin Ian King &lt;colin.i.king@gmail.com&gt;
Link: https://lore.kernel.org/r/20220624081409.14760-1-colin.i.king@gmail.com
[yilun.xu@intel.com: add the Fixes tag]
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: microchip-spi: add Microchip MPF FPGA manager</title>
<updated>2022-06-24T04:12:31+00:00</updated>
<author>
<name>Ivan Bornyakov</name>
<email>i.bornyakov@metrotek.ru</email>
</author>
<published>2022-06-23T16:32:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=5f8d4a9008307e0bf210906948953386935d361c'/>
<id>5f8d4a9008307e0bf210906948953386935d361c</id>
<content type='text'>
Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Signed-off-by: Ivan Bornyakov &lt;i.bornyakov@metrotek.ru&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220623163248.3672-4-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Signed-off-by: Ivan Bornyakov &lt;i.bornyakov@metrotek.ru&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220623163248.3672-4-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: fpga-mgr: support bitstream offset in image buffer</title>
<updated>2022-06-24T04:11:18+00:00</updated>
<author>
<name>Ivan Bornyakov</name>
<email>i.bornyakov@metrotek.ru</email>
</author>
<published>2022-06-23T16:32:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3cc624beba6310a8a534fb00841f22445a200d54'/>
<id>3cc624beba6310a8a534fb00841f22445a200d54</id>
<content type='text'>
At the moment FPGA manager core loads to the device entire image
provided to fpga_mgr_load(). But it is not always whole FPGA image
buffer meant to be written to the device. In particular, .dat formatted
image for Microchip MPF contains meta info in the header that is not
meant to be written to the device. This is issue for those low level
drivers that loads data to the device with write() fpga_manager_ops
callback, since write() can be called in iterator over scatter-gather
table, not only linear image buffer. On the other hand, write_sg()
callback is provided with whole image in scatter-gather form and can
decide itself which part should be sent to the device.

Add header_size and data_size to the fpga_image_info struct, add
skip_header to the fpga_manager_ops struct and adjust fpga_mgr_write()
callers with respect to them.

  * info-&gt;header_size indicates part at the beginning of image buffer
    that contains some meta info. It is optional and can be 0,
    initialized with mops-&gt;initial_header_size.

  * mops-&gt;skip_header tells fpga-mgr core whether write should start
    from the beginning of image buffer or at the offset of header_size.

  * info-&gt;data_size is the size of bitstream data that is meant to be
    written to the device. It is also optional and can be 0, which
    means bitstream data is up to the end of image buffer.

Also add parse_header() callback to fpga_manager_ops, which purpose is
to set info-&gt;header_size and info-&gt;data_size. At least
initial_header_size bytes of image buffer will be passed into
parse_header() first time. If it is not enough, parse_header() should
set desired size into info-&gt;header_size and return -EAGAIN, then it will
be called again with greater part of image buffer on the input.

Suggested-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Ivan Bornyakov &lt;i.bornyakov@metrotek.ru&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220623163248.3672-2-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At the moment FPGA manager core loads to the device entire image
provided to fpga_mgr_load(). But it is not always whole FPGA image
buffer meant to be written to the device. In particular, .dat formatted
image for Microchip MPF contains meta info in the header that is not
meant to be written to the device. This is issue for those low level
drivers that loads data to the device with write() fpga_manager_ops
callback, since write() can be called in iterator over scatter-gather
table, not only linear image buffer. On the other hand, write_sg()
callback is provided with whole image in scatter-gather form and can
decide itself which part should be sent to the device.

Add header_size and data_size to the fpga_image_info struct, add
skip_header to the fpga_manager_ops struct and adjust fpga_mgr_write()
callers with respect to them.

  * info-&gt;header_size indicates part at the beginning of image buffer
    that contains some meta info. It is optional and can be 0,
    initialized with mops-&gt;initial_header_size.

  * mops-&gt;skip_header tells fpga-mgr core whether write should start
    from the beginning of image buffer or at the offset of header_size.

  * info-&gt;data_size is the size of bitstream data that is meant to be
    written to the device. It is also optional and can be 0, which
    means bitstream data is up to the end of image buffer.

Also add parse_header() callback to fpga_manager_ops, which purpose is
to set info-&gt;header_size and info-&gt;data_size. At least
initial_header_size bytes of image buffer will be passed into
parse_header() first time. If it is not enough, parse_header() should
set desired size into info-&gt;header_size and return -EAGAIN, then it will
be called again with greater part of image buffer on the input.

Suggested-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Ivan Bornyakov &lt;i.bornyakov@metrotek.ru&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220623163248.3672-2-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-pr-ip: fix unsigned comparison with less than zero</title>
<updated>2022-06-10T07:48:23+00:00</updated>
<author>
<name>Marco Pagani</name>
<email>marpagan@redhat.com</email>
</author>
<published>2022-06-09T14:05:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2df84a757d87fd62869fc401119d429735377ec5'/>
<id>2df84a757d87fd62869fc401119d429735377ec5</id>
<content type='text'>
Fix the "comparison with less than zero" warning reported by
cppcheck for the unsigned (size_t) parameter count of the
alt_pr_fpga_write() function.

Fixes: d201cc17a8a3 ("fpga pr ip: Core driver support for Altera Partial Reconfiguration IP")
Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Marco Pagani &lt;marpagan@redhat.com&gt;
Link: https://lore.kernel.org/r/20220609140520.42662-1-marpagan@redhat.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix the "comparison with less than zero" warning reported by
cppcheck for the unsigned (size_t) parameter count of the
alt_pr_fpga_write() function.

Fixes: d201cc17a8a3 ("fpga pr ip: Core driver support for Altera Partial Reconfiguration IP")
Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Marco Pagani &lt;marpagan@redhat.com&gt;
Link: https://lore.kernel.org/r/20220609140520.42662-1-marpagan@redhat.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: Directly use ida_alloc()/free()</title>
<updated>2022-06-08T09:04:39+00:00</updated>
<author>
<name>keliu</name>
<email>liuke94@huawei.com</email>
</author>
<published>2022-05-27T08:59:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a5e3d775d088658a0bd734eebd07283c9ac79c17'/>
<id>a5e3d775d088658a0bd734eebd07283c9ac79c17</id>
<content type='text'>
Use ida_alloc()/ida_free() instead of deprecated
ida_simple_get()/ida_simple_remove() .

Signed-off-by: keliu &lt;liuke94@huawei.com&gt;
Link: https://lore.kernel.org/r/20220527085915.2798928-1-liuke94@huawei.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use ida_alloc()/ida_free() instead of deprecated
ida_simple_get()/ida_simple_remove() .

Signed-off-by: keliu &lt;liuke94@huawei.com&gt;
Link: https://lore.kernel.org/r/20220527085915.2798928-1-liuke94@huawei.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: m10bmc-sec: add max10 secure update functions</title>
<updated>2022-06-08T09:04:39+00:00</updated>
<author>
<name>Russ Weight</name>
<email>russell.h.weight@intel.com</email>
</author>
<published>2022-06-06T16:00:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=5cd339b370e29b04b85fbb83f40496991465318e'/>
<id>5cd339b370e29b04b85fbb83f40496991465318e</id>
<content type='text'>
Create firmware upload ops and call the Firmware Upload support of the
Firmware Loader subsystem to enable FPGA image uploads for secure
updates of BMC images, FPGA images, etc.

Tested-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Link: https://lore.kernel.org/r/20220606160038.846236-6-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Create firmware upload ops and call the Firmware Upload support of the
Firmware Loader subsystem to enable FPGA image uploads for secure
updates of BMC images, FPGA images, etc.

Tested-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Link: https://lore.kernel.org/r/20220606160038.846236-6-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: m10bmc-sec: expose max10 canceled keys in sysfs</title>
<updated>2022-06-08T09:04:38+00:00</updated>
<author>
<name>Russ Weight</name>
<email>russell.h.weight@intel.com</email>
</author>
<published>2022-06-06T16:00:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=7f03d84a672d87630448339a8a0e1d689f6980f9'/>
<id>7f03d84a672d87630448339a8a0e1d689f6980f9</id>
<content type='text'>
Extend the MAX10 BMC Secure Update driver to provide sysfs files to
expose the 128 bit code signing key (CSK) cancellation vectors. These use
the standard bitmap list format (e.g. 1,2-6,9).

Each CSK is assigned an ID, a number between 0-127, during the signing
process. CSK ID cancellation information is stored in 128-bit fields in
write-once locations in flash.  The cancellation of a CSK can be used
to prevent the card from being rolled back to older images that were
signed with a CSK that is now cancelled.

Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Tested-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Link: https://lore.kernel.org/r/20220606160038.846236-5-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Extend the MAX10 BMC Secure Update driver to provide sysfs files to
expose the 128 bit code signing key (CSK) cancellation vectors. These use
the standard bitmap list format (e.g. 1,2-6,9).

Each CSK is assigned an ID, a number between 0-127, during the signing
process. CSK ID cancellation information is stored in 128-bit fields in
write-once locations in flash.  The cancellation of a CSK can be used
to prevent the card from being rolled back to older images that were
signed with a CSK that is now cancelled.

Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Tested-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Link: https://lore.kernel.org/r/20220606160038.846236-5-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
