linux-stable.git/drivers/fpga, branch v5.10

fpga: Specify HAS_IOMEM dependency for FPGA_DFL

2020-12-01T17:46:24+00:00

Because dfl.c uses the 'devm_ioremap', 'devm_iounmap',
'devm_ioremap_resource', and 'devm_platform_ioremap_resource'
functions, it should depend on HAS_IOMEM.

This fixes make allyesconfig under UML (ARCH=um), which doesn't provide
HAS_IOMEM.

[mdf@kernel.org: Removed "drivers: " in commit message]
Fixes: 89eb35e810a8 ("fpga: dfl: map feature mmio resources in their own feature drivers")
Signed-off-by: David Gow 
Signed-off-by: Moritz Fischer 
Link: https://lore.kernel.org/r/20201122001549.107023-2-mdf@kernel.org
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: create a dfl bus type to support DFL devices

2020-09-10T03:28:16+00:00

A new bus type "dfl" is introduced for private features which are not
initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
private features could be handled by separate driver modules.

DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on
enumeration. DFL drivers could be registered on this bus to match these
DFL devices. They are matched by dfl type & feature_id.

[mdf@kernel.org: Add missing Documentation part to MAINTAINERS file]

Signed-off-by: Xu Yilun 
Signed-off-by: Wu Hao 
Signed-off-by: Matthew Gerlach 
Signed-off-by: Russ Weight 
Reviewed-by: Tom Rix 
Acked-by: Wu Hao 
Signed-off-by: Moritz Fischer

fpga: fpga-region: Cleanup an outdated comment

2020-09-05T03:27:45+00:00

Clean up an outdated comment claiming FPGA regions implement devicetree
support for reprogramming FPGAs.

Signed-off-by: Moritz Fischer

fpga: dfl: map feature mmio resources in their own feature drivers

2020-08-31T00:15:58+00:00

This patch makes preparation for modularization of DFL sub feature
drivers.

DFL based FPGA devices may contain some IP blocks which are already
supported by kernel, most of them are supported by platform device
drivers. We could create platform devices for these IP blocks and get them
supported by these drivers.

An important issue is that platform device drivers usually requests mmio
resources on probe. But now DFL mmio is mapped in DFL bus driver (e.g.
dfl-pci) as a whole region. Then platform device drivers for sub features
can't request their own mmio resources again. This is what the patch
trying to resolve.

This patch changes the DFL enumeration. DFL bus driver will unmap mmio
resources after first step enumeration and pass enumeration info to DFL
framework. Then DFL framework will map the mmio resources again, do 2nd
step enumeration, and also unmap the mmio resources. In this way, sub
feature drivers could then request their own mmio resources as needed.

An exception is that mmio resource of FIU headers are still mapped in DFL
bus driver. The FIU headers have some fundamental functions (sriov set,
port enable/disable) needed for DFL bus devices and other sub features.
They should not be unmapped as long as DFL bus device is alive.

Signed-off-by: Xu Yilun 
Signed-off-by: Wu Hao 
Signed-off-by: Matthew Gerlach 
Signed-off-by: Russ Weight 
Reviewed-by: Tom Rix 
Acked-by: Wu Hao 
Signed-off-by: Moritz Fischer

fpga manager: xilinx-spi: provide better diagnostics on programming failure

2020-08-31T00:09:05+00:00

When the DONE pin does not go high after programming to confirm programming
success, the INIT_B pin provides some info on the reason. Use it if
available to provide a more explanatory error message.

Reviewed-by: Tom Rix 
Signed-off-by: Luca Ceresoli 
Signed-off-by: Moritz Fischer

fpga manager: xilinx-spi: add error checking after gpiod_get_value()

2020-08-31T00:08:57+00:00

Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.

Fix by checking for negative error values.

Reported-by: Tom Rix 
Reviewed-by: Tom Rix 
Signed-off-by: Luca Ceresoli 
Signed-off-by: Moritz Fischer

fpga manager: xilinx-spi: fix write_complete timeout handling

2020-08-31T00:06:50+00:00

If this routine sleeps because it was scheduled out, it might miss DONE
going asserted and consider it a timeout. This would potentially make the
code return an error even when programming succeeded. Rewrite the loop to
always check DONE after checking if timeout expired so this cannot happen
anymore.

While there, also add error checking for gpiod_get_value(). Also avoid
checking the DONE GPIO in two places, which would make the error-checking
code duplicated and more annoying.

The new loop it written to still guarantee that we apply 8 extra CCLK
cycles after DONE has gone asserted, which is required by the hardware.

Reported-by: Tom Rix 
Reviewed-by: Tom Rix 
Signed-off-by: Luca Ceresoli 
Signed-off-by: Moritz Fischer

fpga manager: xilinx-spi: remove final dot from dev_err() strings

2020-08-31T00:04:18+00:00

Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.

Reviewed-by: Tom Rix 
Signed-off-by: Luca Ceresoli 
Signed-off-by: Moritz Fischer

fpga manager: xilinx-spi: remove stray comment

2020-08-20T04:10:47+00:00

Remove comment committed by mistake.

Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during write_init")
Signed-off-by: Luca Ceresoli 
Signed-off-by: Moritz Fischer

fpga: dfl: change data type of feature id to u16

2020-08-20T04:05:47+00:00

The feature id is stored in a 12 bit field in DFH. So a u16 variable is
enough for feature id.

This patch changes all feature id related places to fit u16.

Signed-off-by: Xu Yilun 
Reviewed-by: Tom Rix 
Acked-by: Wu Hao 
Signed-off-by: Moritz Fischer