linux-stable.git/drivers/fpga, branch v4.12.2

fpga fr br: update supported version numbers

2017-04-26T09:38:56+00:00

The value in the version register of the altera freeze bridge
controller changed from the beta value of 2 to the
value of 0xad000003 in the official release of the IP.
This patch supports the old and new version numbers, and the
driver's probe function will fail if neither of the supported
versions is found.

Signed-off-by: Matthew Gerlach 
Reviewed-by: Moritz Fischer 
Signed-off-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: region: release FPGA region reference in error path

2017-04-26T09:38:56+00:00

If fpga_region_get_manager() fails in fpga_region_program_fpga(), a
reference to the fpga_manager instance previously acquired through
fpga_region_get() is retained. Make sure to properly release it in the
error case by using a separate jump label which will call
fpga_region_put() in before returning.

Signed-off-by: Tobias Klauser 
Acked-by: Moritz Fischer 
Signed-off-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga altera-hps2fpga: disable/unprepare clock on error in alt_fpga_bridge_probe()

2017-04-26T09:38:56+00:00

If either _alt_hps2fpga_enable_set() or fpga_bridge_register() fail in
alt_fpga_bridge_probe(), the clock remains enabled and prepared. Also,
in the error path for _alt_hps2fpga_enable_set() a call to
fpga_bridge_unregister() is made even though the bridge was not
registered yet.

Remove the unnecessary call to fpga_bridge_unregister() and call
clk_disable_unprepare() in both error paths in order to make sure the
clock gets properly disabled and unprepared.

Signed-off-by: Tobias Klauser 
Acked-by: Moritz Fischer 
Signed-off-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: Add support for Xilinx LogiCORE PR Decoupler

2017-04-08T15:50:36+00:00

This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.

Signed-off-by: Moritz Fischer 
Signed-off-by: Michal Simek 
Cc: Sören Brinkmann 
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

2017-04-08T15:45:28+00:00

This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

2017-04-08T15:45:28+00:00

Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: add config complete timeout

2017-04-08T15:45:28+00:00

Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.

Signed-off-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga manager: Add Xilinx slave serial SPI driver

2017-04-08T15:45:28+00:00

The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.

Signed-off-by: Anatolij Gustschin 
Acked-by: Michal Simek 
Reviewed-by: Moritz Fischer 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: altera_freeze_bridge: Constify ops

2017-04-08T15:45:28+00:00

The ops are not changing, make them const.

Signed-off-by: Moritz Fischer 
Cc: Alan Tull 
Cc: linux-kernel@vger.kernel.org
Cc: linux-fpga@vger.kernel.org
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: bridge: Replace open-coded list_for_each + list_entry

2017-03-17T06:10:48+00:00

Replaces open-coded list_for_each() + list_entry() with macro
list_for_each_entry()

Signed-off-by: Moritz Fischer 
Cc: linux-fpga@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman