linux-stable.git/drivers/edac, branch master Linux kernel stable tree Merge tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2026-08-18T21:02:15+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-18T21:02:15+00:00 8dcef8882aad8f1b8668d1c39968cde99312aa3c Pull x86 MSR updates from Ingo Molnar: - Streamline the x86 MSR handling APIs along the 64-bit variants, simplifying the interfaces. Removal of the old APIs is planned for the next cycle, to reduce churn & integration pain (Juergen Gross) * tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) x86/mce: Work around build warning after MSR-interface switch cpufreq: Stop using 32-bit MSR interfaces x86/featctl: Stop using 32-bit MSR interfaces KVM/x86: Stop using 32-bit MSR interfaces x86/mtrr: Stop using 32-bit MSR interfaces acpi: Stop using 32-bit MSR interfaces powercap: Stop using 32-bit MSR interfaces thermal/intel: Stop using 32-bit MSR interfaces x86/olpc: Stop using 32-bit MSR interfaces x86/hyperv: Stop using 32-bit MSR interfaces hwmon: Stop using 32-bit MSR interfaces EDAC: Stop using 32-bit MSR interfaces x86/cpu: Stop using 32-bit MSR interfaces x86/apic: Stop using 32-bit MSR interfaces x86/resctrl: Stop using 32-bit MSR interfaces x86/tsc: Stop using 32-bit MSR interfaces x86/amd: Stop using 32-bit MSR interfaces x86/pci: Stop using 32-bit MSR interfaces x86/hygon: Stop using 32-bit MSR interfaces x86/mce: Stop using 32-bit MSR interfaces ... 
Pull x86 MSR updates from Ingo Molnar:

 - Streamline the x86 MSR handling APIs along the 64-bit variants,
   simplifying the interfaces.

   Removal of the old APIs is planned for the next cycle, to reduce
   churn & integration pain (Juergen Gross)

* tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits)
  x86/mce: Work around build warning after MSR-interface switch
  cpufreq: Stop using 32-bit MSR interfaces
  x86/featctl: Stop using 32-bit MSR interfaces
  KVM/x86: Stop using 32-bit MSR interfaces
  x86/mtrr: Stop using 32-bit MSR interfaces
  acpi: Stop using 32-bit MSR interfaces
  powercap: Stop using 32-bit MSR interfaces
  thermal/intel: Stop using 32-bit MSR interfaces
  x86/olpc: Stop using 32-bit MSR interfaces
  x86/hyperv: Stop using 32-bit MSR interfaces
  hwmon: Stop using 32-bit MSR interfaces
  EDAC: Stop using 32-bit MSR interfaces
  x86/cpu: Stop using 32-bit MSR interfaces
  x86/apic: Stop using 32-bit MSR interfaces
  x86/resctrl: Stop using 32-bit MSR interfaces
  x86/tsc: Stop using 32-bit MSR interfaces
  x86/amd: Stop using 32-bit MSR interfaces
  x86/pci: Stop using 32-bit MSR interfaces
  x86/hygon: Stop using 32-bit MSR interfaces
  x86/mce: Stop using 32-bit MSR interfaces
  ...
Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c files) 2026-07-03T05:38:17+00:00 Uwe Kleine-König (The Capable Hub) u.kleine-koenig@baylibre.com 2026-06-30T09:24:36+00:00 995832b2cebe6969d1b42635db698803ee31294d Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> 
Replace the #include of <linux/mod_devicetable.h> by the more specific
<linux/device-id/*.h> where applicable. For most cases the include
can be dropped completely, only a few drivers need one or two headers
added.

Acked-by: Danilo Krummrich <dakr@kernel.org>
Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
EDAC: Stop using 32-bit MSR interfaces 2026-07-02T09:54:53+00:00 Juergen Gross jgross@suse.com 2026-06-29T06:04:54+00:00 3e8ca6691e9d6695e36cafa84217bb8b955face1 The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: Jason Baron <jbaron@akamai.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Yazen Ghannam <yazen.ghannam@amd.com> Cc: linux-edac@vger.kernel.org Link: https://patch.msgid.link/20260629060526.3638272-4-jgross@suse.com 
The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to
be removed. Use the related 64-bit variants instead.

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Jason Baron <jbaron@akamai.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: linux-edac@vger.kernel.org
Link: https://patch.msgid.link/20260629060526.3638272-4-jgross@suse.com
EDAC: Consistently define pci_device_ids using named initializers 2026-05-29T20:28:36+00:00 Uwe Kleine-König (The Capable Hub) u.kleine-koenig@baylibre.com 2026-05-27T06:10:56+00:00 78d86a71de6ea70c6228e7817f3962c618c1eb54 ... and PCI device helpers. The various struct pci_device_id arrays were initialized mostly by one of the PCI_DEVICE macros and then list expressions. The latter aren't easily readable if you're not into PCI. Using named initializers is more explicit and thus easier to parse. Also use PCI_DEVICE* helper macros to assign .vendor, .device, .subvendor and .subdevice where appropriate and skip explicit assignments of 0 (which the compiler takes care of). The secret plan is to make struct pci_device_id::driver_data an anonymous union (similar to https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/ and that requires named initializers. But it's also a nice cleanup on its own. [ bp: Massage commit message. ] Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260527061057.3796383-2-u.kleine-koenig@baylibre.com 
... and PCI device helpers.

The various struct pci_device_id arrays were initialized mostly by one of the
PCI_DEVICE macros and then list expressions. The latter aren't easily readable
if you're not into PCI. Using named initializers is more explicit and thus
easier to parse.

Also use PCI_DEVICE* helper macros to assign .vendor, .device, .subvendor and
.subdevice where appropriate and skip explicit assignments of 0 (which the
compiler takes care of).

The secret plan is to make struct pci_device_id::driver_data an anonymous
union (similar to

  https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/

and that requires named initializers. But it's also a nice cleanup on its own.

  [ bp: Massage commit message. ]

Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://patch.msgid.link/20260527061057.3796383-2-u.kleine-koenig@baylibre.com
EDAC/igen6: Add Intel Nova Lake-H SoC support 2026-05-29T15:34:13+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-05-21T12:38:12+00:00 96780b953bac89bc624c3bf326a090f069d8d277 Nova Lake-H SoCs share similar memory controller registers and IBECC (In-Band ECC) registers with Panther Lake-H SoCs but use a new memory subsystem register for IBECC presence detection. Add Nova Lake-H SoC compute die IDs and create a new configuration structure for Nova Lake-H SoCs to enable EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260521123812.3961038-3-qiuxu.zhuo@intel.com 
Nova Lake-H SoCs share similar memory controller registers and IBECC
(In-Band ECC) registers with Panther Lake-H SoCs but use a new memory
subsystem register for IBECC presence detection.

Add Nova Lake-H SoC compute die IDs and create a new configuration
structure for Nova Lake-H SoCs to enable EDAC support.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Jie Wang <jie.wang@intel.com>
Link: https://patch.msgid.link/20260521123812.3961038-3-qiuxu.zhuo@intel.com
EDAC/igen6: Make registers for detecting IBECC configurable 2026-05-29T15:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-05-21T12:38:11+00:00 407791a6228da6a2a88b046d0bdf85255b444bab Some Intel CPUs with IBECC (In-Band ECC) capability use different registers to indicate IBECC presence. Make IBECC detection registers CPU-model specific and configure them properly for scalable IBECC detection. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260521123812.3961038-2-qiuxu.zhuo@intel.com 
Some Intel CPUs with IBECC (In-Band ECC) capability use different registers
to indicate IBECC presence. Make IBECC detection registers CPU-model
specific and configure them properly for scalable IBECC detection.

No functional changes intended.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Jie Wang <jie.wang@intel.com>
Link: https://patch.msgid.link/20260521123812.3961038-2-qiuxu.zhuo@intel.com
EDAC/imh: Add RRL support for Intel Diamond Rapids server 2026-05-29T15:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-05-21T07:31:12+00:00 bdfc4367e3f516479e0a68c731bea5c6638a6c7e Compared to previous generations, Diamond Rapids RRL (Retry Read error Log) operates at DDR sub-channel granularity and adds an extra register per set. It also increases the CORRERRCNT register width from 4 to 8 bytes while reducing the number of registers from 8 to 4. Add the Diamond Rapids RRL register configuration table and enable support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-9-qiuxu.zhuo@intel.com 
Compared to previous generations, Diamond Rapids RRL (Retry Read error Log)
operates at DDR sub-channel granularity and adds an extra register per set.
It also increases the CORRERRCNT register width from 4 to 8 bytes while
reducing the number of registers from 8 to 4.

Add the Diamond Rapids RRL register configuration table and enable support.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Link: https://patch.msgid.link/20260521073112.3881223-9-qiuxu.zhuo@intel.com
EDAC/{skx_common,i10nm}: Prepare RRL for sub-channel granularity 2026-05-29T15:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-05-21T07:31:11+00:00 4742ae4d82454af4eb21c9eefb17c5e80a08d392 To prepare for enabling Diamond Rapids server RRL (Retry Read error Log), which operates at sub-channel granularity by converting struct res_config::reg_rrl_ddr from a single pointer to an array (reg_rrl_ddr[2]) and updating all users in i10nm_edac and skx_common accordingly. Initialize only reg_rrl_ddr[0] for existing platforms and prepare for supporting two RRL set groups per DDR channel (one per sub-channel) when present. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-8-qiuxu.zhuo@intel.com 
To prepare for enabling Diamond Rapids server RRL (Retry Read error Log),
which operates at sub-channel granularity by converting struct
res_config::reg_rrl_ddr from a single pointer to an array (reg_rrl_ddr[2])
and updating all users in i10nm_edac and skx_common accordingly.

Initialize only reg_rrl_ddr[0] for existing platforms and prepare for
supporting two RRL set groups per DDR channel (one per sub-channel)
when present.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Link: https://patch.msgid.link/20260521073112.3881223-8-qiuxu.zhuo@intel.com
EDAC/skx_common: Add SubChannel support to ADXL decode 2026-05-29T15:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-05-21T07:31:10+00:00 5b33d5a7be01000014f81e426ff20c3a20b5d9b0 Diamond Rapids server RRL (Retry Read error Log) operates at sub-channel granularity. Add SubChannel support to ADXL decoding in preparation for enabling this feature. Also introduce adxl_component_required() to validate mandatory ADXL components to improve code readability. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-7-qiuxu.zhuo@intel.com 
Diamond Rapids server RRL (Retry Read error Log) operates at sub-channel
granularity. Add SubChannel support to ADXL decoding in preparation for
enabling this feature.

Also introduce adxl_component_required() to validate mandatory ADXL
components to improve code readability.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Link: https://patch.msgid.link/20260521073112.3881223-7-qiuxu.zhuo@intel.com
EDAC/{skx_common,i10nm}: Move RRL handling to common code 2026-05-29T15:34:12+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2026-05-21T07:31:09+00:00 8998a4a646471dc218f6499c5580e252891ccaa4 Move RRL (Retry Read error Log) handling from i10nm_edac to skx_common so it can be shared across EDAC drivers (e.g. imh_edac). - Move RRL enable/disable and log dumping helpers to skx_common to avoid code duplication and enable reuse by other drivers. - Export skx_enable_rrl() and skx_show_rrl() so common RRL handling can be used by i10nm_edac and imh_edac. No functional change intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-6-qiuxu.zhuo@intel.com 
Move RRL (Retry Read error Log)  handling from i10nm_edac to skx_common
so it can be shared across EDAC drivers (e.g. imh_edac).

- Move RRL enable/disable and log dumping helpers to skx_common
  to avoid code duplication and enable reuse by other drivers.

- Export skx_enable_rrl() and skx_show_rrl()
  so common RRL handling can be used by i10nm_edac and imh_edac.

No functional change intended.

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Link: https://patch.msgid.link/20260521073112.3881223-6-qiuxu.zhuo@intel.com