linux-stable.git/drivers/dma/Makefile, branch linux-2.6.33.y

ppc440spe-adma: adds updated ppc440spe adma driver

2009-12-12T04:24:44+00:00

This patch adds new version of the PPC440SPe ADMA driver.

Signed-off-by: Yuri Tikhonov 
Signed-off-by: Anatolij Gustschin 
Signed-off-by: Dan Williams

Add COH 901 318 DMA block driver v5

2009-11-20T06:45:19+00:00

This patch adds support for the ST-Ericsson COH 901 318 DMA block,
found in the U300 series platforms. It registers a DMA slave for
device I/O and also a memcpy slave for memcpy.

Signed-off-by: Linus Walleij 
Acked-by: Maciej Sosnowski 
Signed-off-by: Dan Williams

dmaengine: sh: Add Support SuperH DMA Engine driver

2009-09-09T00:56:02+00:00

This supported all DMA channels, and it was tested in SH7722,
SH7780, SH7785 and SH7763.
This can not use with SH DMA API.

Signed-off-by: Nobuhiro Iwamatsu 
Reviewed-by: Matt Fleming 
Acked-by: Maciej Sosnowski 
Acked-by: Paul Mundt 
Signed-off-by: Dan Williams

Merge branch 'ioat' into dmaengine

2009-09-09T00:52:57+00:00

Merge commit 'v2.6.31-rc1' into dmaengine

2009-09-08T21:32:24+00:00

ioat: move to drivers/dma/ioat/

2009-07-28T21:32:12+00:00

When first created the ioat driver was the only inhabitant of
drivers/dma/.  Now, it is the only multi-file (more than a .c and a .h)
driver in the directory.  Moving it to an ioat/ subdirectory allows the
naming convention to be cleaned up, and allows for future splitting of
the source files by hardware version (v1, v2, and v3).

Signed-off-by: Maciej Sosnowski 
Signed-off-by: Dan Williams

dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller

2009-07-23T05:41:27+00:00

This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on
at91sam9rl chip. It will be used on other products in the future.

This first release covers only the memory-to-memory tranfer type. This is the
only tranfer type supported by this chip.  On other products, it will be used
also for peripheral DMA transfer (slave API support to come).

I used dmatest client without problem in different configurations to test it.

Full documentation for this controller can be found in the SAM9RL datasheet:
http://www.atmel.com/dyn/products/product_card.asp?part_id=4243

Signed-off-by: Nicolas Ferre 
Acked-by: Maciej Sosnowski 
Signed-off-by: Dan Williams

DMA: TXx9 Soc DMA Controller driver

2009-06-17T10:06:25+00:00

This patch adds support for the integrated DMAC of the TXx9 family.

Signed-off-by: Atsushi Nemoto 
Acked-by: Dan Williams 
Signed-off-by: Ralf Baechle

i.MX31: Image Processing Unit DMA and IRQ drivers

2009-01-19T22:36:21+00:00

i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.

IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.

Acked-by: Sascha Hauer 
Signed-off-by: Guennadi Liakhovetski 
Signed-off-by: Dan Williams

dmaengine: Driver for the Synopsys DesignWare DMA controller

2008-07-08T18:59:42+00:00

This adds a driver for the Synopsys DesignWare DMA controller (aka
DMACA on AVR32 systems.) This DMA controller can be found integrated
on the AT32AP7000 chip and is primarily meant for peripheral DMA
transfer, but can also be used for memory-to-memory transfers.

This patch is based on a driver from David Brownell which was based on
an older version of the DMA Engine framework. It also implements the
proposed extensions to the DMA Engine API for slave DMA operations.

The dmatest client shows no problems, but there may still be room for
improvement performance-wise. DMA slave transfer performance is
definitely "good enough"; reading 100 MiB from an SD card running at ~20
MHz yields ~7.2 MiB/s average transfer rate.

Full documentation for this controller can be found in the Synopsys
DW AHB DMAC Databook:

http://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf

The controller has lots of implementation options, so it's usually a
good idea to check the data sheet of the chip it's intergrated on as
well. The AT32AP7000 data sheet can be found here:

http://www.atmel.com/dyn/products/datasheets.asp?family_id=682


Changes since v4:
  * Use client_count instead of dma_chan_is_in_use()
  * Add missing include
  * Unmap buffers unless client told us not to

Changes since v3:
  * Update to latest DMA engine and DMA slave APIs
  * Embed the hw descriptor into the sw descriptor
  * Clean up and update MODULE_DESCRIPTION, copyright date, etc.

Changes since v2:
  * Dequeue all pending transfers in terminate_all()
  * Rename dw_dmac.h -> dw_dmac_regs.h
  * Define and use controller-specific dma_slave data
  * Fix up a few outdated comments
  * Define hardware registers as structs (doesn't generate better
    code, unfortunately, but it looks nicer.)
  * Get number of channels from platform_data instead of hardcoding it
    based on CONFIG_WHATEVER_CPU.
  * Give slave clients exclusive access to the channel

Acked-by: Maciej Sosnowski ,
Signed-off-by: Haavard Skinnemoen 
Signed-off-by: Dan Williams