linux-stable.git/drivers/crypto/caam/ctrl.c, branch linux-4.5.y

crypto: caam - make write transactions bufferable on PPC platforms

2016-01-25T13:47:44+00:00

Previous change (see "Fixes" tag) to the MCFGR register
clears AWCACHE[0] ("bufferable" AXI3 attribute) (which is "1" at POR).

This makes all writes non-bufferable, causing a ~ 5% performance drop
for PPC-based platforms.

Rework previous change such that MCFGR[AWCACHE]=4'b0011
(bufferable + cacheable) for all platforms.
Note: For ARM-based platforms, AWCACHE[0] is ignored
by the interconnect IP.

Cc:  # 4.3+
Fixes: f10967495144 ("crypto: caam - fix snooping for write transactions")
Signed-off-by: Horia Geant? 
Signed-off-by: Herbert Xu

crypto: caam - Use the preferred style for memory allocations

2015-08-24T14:07:42+00:00

"The preferred form for passing a size of a struct is the following:

        p = kmalloc(sizeof(*p), ...);
....

The preferred form for allocating a zeroed array is the following:

        p = kcalloc(n, sizeof(...), ...); "

,so do as suggested.

Signed-off-by: Fabio Estevam 
Reviewed-by: Horia Geant? 
Signed-off-by: Herbert Xu

crypto: caam - Propagate the real error code in caam_probe

2015-08-24T14:07:41+00:00

Instead of propagating a 'fake' error code, just propagate the real
one in the case of caam_drv_identify_clk() failure.

Signed-off-by: Fabio Estevam 
Reviewed-by: Horia Geant? 
Signed-off-by: Herbert Xu

crypto: caam - Fix the error handling in caam_probe

2015-08-24T14:07:39+00:00

In the error path we should disable the resources that were previously
acquired, so fix the error handling accordingly.

Signed-off-by: Fabio Estevam 
Reviewed-by: Horia Geant? 
Signed-off-by: Herbert Xu

crypto: caam - fix writing to JQCR_MS when using service interface

2015-08-24T14:07:38+00:00

Most significant part of JQCR (Job Queue Control Register) contains
bits that control endianness: ILE - Immediate Little Endian,
DWS - Double Word Swap.
The bits are automatically set by the Job Queue Controller HW.

Unfortunately these bits are cleared in SW when submitting descriptors
via the register-based service interface.
>From LS1021A:
JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)

This would cause problems on little endian caam for descriptors
containing immediata data or double-word pointers.
Currently there is no problem since the only descriptors ran through
this interface are the ones that (un)instantiate RNG.

Signed-off-by: Horia Geant? 
Signed-off-by: Herbert Xu

crypto: caam - add support for LS1021A

2015-08-18T02:30:39+00:00

LS1021A is a QorIQ SoC having little endian CAAM.

There are a few differences b/w QorIQ and i.MX from CAAM perspective:

1. i.MX platforms are somewhat special wrt. 64-bit registers:
-big endian format at 64-bit level: MSW at address+0 and LSW at address+4
-little endian format at 32-bit level (within MSW and LSW)
and thus need special handling.

2. No CCM (clock controller module) for QorIQ.
No CAAM clocks to enable / disable.

A new Kconfig option - CRYPTO_DEV_FSL_CAAM_LE - is added to indicate
CAAM is little endian (*). It is hidden from the user (to avoid
misconfiguration); when adding support for a new platform with LE CAAM,
either the Kconfig needs to be updated or the corresponding defconfig
needs to indicate that CAAM is LE.
(*) Using a DT property to provide CAAM endianness would not allow
for the ifdeffery.

In order to keep changes to a minimum, the following changes
are postponed:
-endianness fix of the last word in the S/G (rsvd2, bpid, offset),
fields are always 0 anyway;
-S/G format fix for i.MX7 (yes, i.MX7 support was not added yet,
but still...)

Signed-off-by: Horia Geant? 
Signed-off-by: Herbert Xu

crypto: caam - Remove unneeded 'ret' variable

2015-08-13T07:13:29+00:00

Variable 'ret' is only used for returning the value 0.

We can make it simpler and just return 0 instead.

The semantic patch that makes this change is available
in scripts/coccinelle/misc/returnvar.cocci.

Signed-off-by: Fabio Estevam 
Signed-off-by: Herbert Xu

crypto: caam - Enable and disable clocks on Freescale i.MX platforms

2015-08-10T15:18:56+00:00

ARM-based systems may disable clocking to the CAAM device on the
Freescale i.MX platform for power management purposes.  This patch
enables the required clocks when the CAAM module is initialized and
disables the required clocks when the CAAM module is shut down.

Signed-off-by: Victoria Milhoan 
Tested-by: Horia Geantă 
Signed-off-by: Herbert Xu

crypto: caam - Add setbits32/clrbits32/clrsetbits primitives for ARM compatibility

2015-08-10T15:18:56+00:00

Add set/clear 32-bit primitives for compatibility with ARM devices since
the primitives were previously only defined for the Power architecture.

Signed-off-by: Victoria Milhoan 
Tested-by: Horia Geantă 
Signed-off-by: Herbert Xu

crypto: caam - fix RNG init descriptor ret. code checking

2015-07-20T07:53:42+00:00

When successful, the descriptor that performs RNG initialization
is allowed to return a status code of 7000_0000h, since last command
in the descriptor is a JUMP HALT.

Signed-off-by: Horia Geant? 
Signed-off-by: Herbert Xu