linux-stable.git/drivers/clocksource/timer-sun5i.c, branch linux-3.19.y Linux kernel stable tree clockevents: sun5i: Fix setup_irq init sequence 2015-04-13T12:03:49+00:00 Yongbae Park yongbae2@gmail.com 2015-03-03T04:05:48+00:00 0e1e3b03a3edcc2fd5a56fbbbc03d6eec07146c9 commit 1096be084ac59927158ce80ff1d31c33eed0e565 upstream. The interrupt is enabled before the handler is set. Even this bug did not appear, it is potentially dangerous as it can lead to a NULL pointer dereference. Fix the error by enabling the interrupt after clockevents_config_and_register() is called. Signed-off-by: Yongbae Park <yongbae2@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit 1096be084ac59927158ce80ff1d31c33eed0e565 upstream.

The interrupt is enabled before the handler is set. Even this bug
did not appear, it is potentially dangerous as it can lead to a
NULL pointer dereference.

Fix the error by enabling the interrupt after
clockevents_config_and_register() is called.

Signed-off-by: Yongbae Park <yongbae2@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
clocksource: sun5i: Add support for reset controller 2014-04-22T11:56:50+00:00 Maxime Ripard maxime.ripard@free-electrons.com 2014-04-17T09:06:45+00:00 e50a00be5c420b4f28836dec281cdde4bed832a2 The Allwinner A31 that uses this timer has the timer IP asserted in reset. Add an optional reset property to the DT, and deassert the timer from reset if it's there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource: Timer-sun5i: Switch to sched_clock_register() 2014-01-19T12:23:23+00:00 Stephen Boyd sboyd@codeaurora.org 2014-01-17T01:38:06+00:00 00e2bcd6d35f59fce7fa0e76e24d08f74c6a8506 The 32-bit sched_clock() interface supports 64 bits since 3.13-rc1. Upgrade to the 64-bit function to allow us to remove the 32-bit registration interface. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1389922686-6249-1-git-send-email-sboyd@codeaurora.org Signed-off-by: Ingo Molnar <mingo@kernel.org> 
The 32-bit sched_clock() interface supports 64 bits since
3.13-rc1. Upgrade to the 64-bit function to allow us to remove
the 32-bit registration interface.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1389922686-6249-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
clocksource: Add Allwinner SoCs HS timers driver 2013-12-11T10:37:50+00:00 Maxime Ripard maxime.ripard@free-electrons.com 2013-11-07T11:01:48+00:00 67905540e8b8eaf51e621cfd2ef15641d6d5b9a7 Most of the Allwinner SoCs (at this time, all but the A10) also have a High Speed timers that are not using the 24MHz oscillator as a source but rather the AHB clock running much faster. The IP is slightly different between the A10s/A13 and the one used in the A20/A31, since the latter have 4 timers available, while the former have only 2 of them. [dlezcano] : Fixed conflict with b788beda "Order Kconfig options alphabetically" Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.

[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
		alphabetically"

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>