linux-stable.git/drivers/clocksource/arm_arch_timer.c, branch linux-4.9.y

arm64: arch_timer: Add workaround for ARM erratum 1188873

2022-04-12T05:52:15+00:00

commit 95b861a4a6d94f64d5242605569218160ebacdbe upstream.

When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.

This only affects versions r0p0, r1p0 and r2p0 of the CPU.

Acked-by: Mark Rutland 
Signed-off-by: Marc Zyngier 
Signed-off-by: Catalin Marinas 
Signed-off-by: James Morse 
Signed-off-by: Greg Kroah-Hartman

arm64: arch_timer: Add erratum handler for CPU-specific capability

2022-04-12T05:52:14+00:00

commit 0064030c6fd4ca6cfab42de037b2a89445beeead upstream.

Should we ever have a workaround for an erratum that is detected using
a capability and affecting a particular CPU, it'd be nice to have
a way to probe them directly.

Acked-by: Thomas Gleixner 
Signed-off-by: Marc Zyngier 
Signed-off-by: James Morse 
Signed-off-by: Greg Kroah-Hartman

arm64: arch_timer: Add infrastructure for multiple erratum detection methods

2022-04-12T05:52:14+00:00

commit 651bb2e9dca6e6dbad3fba5f6e6086a23575b8b5 upstream.

We're currently stuck with DT when it comes to handling errata, which
is pretty restrictive. In order to make things more flexible, let's
introduce an infrastructure that could support alternative discovery
methods. No change in functionality.

Acked-by: Thomas Gleixner 
Reviewed-by: Hanjun Guo 
Signed-off-by: Marc Zyngier 
[ morse: Removed the changes to HiSilicon erratum 161010101, which isn't
  present in v4.9 ]
Signed-off-by: James Morse 
Signed-off-by: Greg Kroah-Hartman

clocksource/drivers/arm_arch_timer: Introduce generic errata handling infrastructure

2022-04-12T05:52:14+00:00

commit 16d10ef29f25aba923779234bb93a451b14d20e6 upstream.

Currently we have code inline in the arch timer probe path to cater for
Freescale erratum A-008585, complete with ifdeffery. This is a little
ugly, and will get worse as we try to add more errata handling.

This patch refactors the handling of Freescale erratum A-008585. Now the
erratum is described in a generic arch_timer_erratum_workaround
structure, and the probe path can iterate over these to detect errata
and enable workarounds.

This will simplify the addition and maintenance of code handling
Hisilicon erratum 161010101.

Signed-off-by: Ding Tianhong 
[Mark: split patch, correct Kconfig, reword commit message]
Signed-off-by: Mark Rutland 
Acked-by: Daniel Lezcano 
Signed-off-by: Daniel Lezcano 
Signed-off-by: James Morse 
Signed-off-by: Greg Kroah-Hartman

clocksource/drivers/arm_arch_timer: Remove fsl-a008585 parameter

2022-04-12T05:52:14+00:00

commit 5444ea6a7f46276876e94ecf8d44615af1ef22f7 upstream.

Having a command line option to flip the errata handling for a
particular erratum is a little bit unusual, and it's vastly superior to
pass this in the DT. By common consensus, it's best to kill off the
command line parameter.

Signed-off-by: Ding Tianhong 
[Mark: split patch, reword commit message]
Signed-off-by: Mark Rutland 
Acked-by: Daniel Lezcano 
Signed-off-by: Daniel Lezcano 
Signed-off-by: James Morse 
Signed-off-by: Greg Kroah-Hartman

clocksource/drivers/arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI

2020-12-29T12:44:58+00:00

[ Upstream commit 8b7770b877d187bfdae1eaf587bd2b792479a31c ]

ARM virtual counter supports event stream, it can only trigger an event
when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 changes,
so the actual period of event stream is 2^(cntkctl_evnti + 1). For example,
when the trigger bit is 0, then virtual counter trigger an event for every
two cycles.

While we're at it, rework the way we compute the trigger bit position
by making it more obvious that when bits [n:n-1] are both set (with n
being the most significant bit), we pick bit (n + 1).

Fixes: 037f637767a8 ("drivers: clocksource: add support for ARM architected timer event stream")
Suggested-by: Marc Zyngier 
Signed-off-by: Keqian Zhu 
Acked-by: Marc Zyngier 
Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/20201204073126.6920-3-zhukeqian1@huawei.com
Signed-off-by: Sasha Levin

clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend

2017-04-12T10:41:16+00:00

[ Upstream commit d8ec7595a013237f82d965dcf981571aeb41855b ]

The ARM specifies that the system counter "must be implemented in an
always-on power domain," and so we try to use the counter as a source of
timekeeping across suspend/resume. Unfortunately, some SoCs (e.g.,
Rockchip's RK3399) do not keep the counter ticking properly when
switched from their high-power clock to the lower-power clock used in
system suspend. Support this quirk by adding a new device tree property.

Signed-off-by: Brian Norris 
Reviewed-by: Douglas Anderson 
Acked-by: Marc Zyngier 
Signed-off-by: Daniel Lezcano 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

arm/arm64: arch_timer: Use archdata to indicate vdso suitability

2016-09-23T16:19:25+00:00

Instead of comparing the name to a magic string, use archdata to
explicitly communicate whether the arch timer is suitable for
direct vdso access.

Acked-by: Will Deacon 
Acked-by: Russell King 
Acked-by: Marc Zyngier 
Signed-off-by: Scott Wood 
Signed-off-by: Will Deacon

arm64: arch_timer: Work around QorIQ Erratum A-008585

2016-09-23T16:19:25+00:00

Erratum A-008585 says that the ARM generic timer counter "has the
potential to contain an erroneous value for a small number of core
clock cycles every time the timer value changes".  Accesses to TVAL
(both read and write) are also affected due to the implicit counter
read.  Accesses to CVAL are not affected.

The workaround is to reread TVAL and count registers until successive
reads return the same value.  Writes to TVAL are replaced with an
equivalent write to CVAL.

The workaround is to reread TVAL and count registers until successive reads
return the same value, and when writing TVAL to retry until counter
reads before and after the write return the same value.

The workaround is enabled if the fsl,erratum-a008585 property is found in
the timer node in the device tree.  This can be overridden with the
clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM
users to enable the workaround until a mechanism is implemented to
automatically communicate this information.

This erratum can be found on LS1043A and LS2080A.

Acked-by: Marc Zyngier 
Signed-off-by: Scott Wood 
[will: renamed read macro to reflect that it's not usually unstable]
Signed-off-by: Will Deacon

clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered

2016-08-01T14:15:53+00:00

The ARM architected timer produces level-triggered interrupts (this
is mandated by the architecture). Unfortunately, a number of
device-trees get this wrong, and expose an edge-triggered interrupt.

Until now, this wasn't too much an issue, as the programming of the
trigger would fail (the corresponding PPI cannot be reconfigured),
and the kernel would be happy with this. But we're about to change
this, and trust DT a lot if the driver doesn't provide its own
trigger information. In that context, the timer breaks badly.

While we do need to fix the DTs, there is also some userspace out
there (kvmtool) that generates the same kind of broken DT on the
fly, and that will completely break with newer kernels.

As a safety measure, and to keep buggy software alive as well as
buying us some time to fix DTs all over the place, let's check
what trigger configuration has been given us by the firmware.
If this is not a level configuration, then we know that the
DT/ACPI configuration is bust, and we pick some defaults which
won't be worse than the existing setup.

Signed-off-by: Marc Zyngier 
Cc: Andrew Lunn 
Cc: Liu Gang 
Cc: Mark Rutland 
Cc: Masahiro Yamada 
Cc: Wenbin Song 
Cc: Mingkai Hu 
Cc: Florian Fainelli 
Cc: Kevin Hilman 
Cc: Daniel Lezcano 
Cc: Michal Simek 
Cc: Jon Hunter 
Cc: arm@kernel.org
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth 
Cc: Jason Cooper 
Cc: Ray Jui 
Cc: "Hou Zhiqiang" 
Cc: Tirumalesh Chalamarla 
Cc: linux-samsung-soc@vger.kernel.org
Cc: Yuan Yao 
Cc: Jan Glauber 
Cc: Gregory Clement 
Cc: linux-amlogic@lists.infradead.org
Cc: soren.brinkmann@xilinx.com
Cc: Rajesh Bhagat 
Cc: Scott Branden 
Cc: Duc Dang 
Cc: Kukjin Kim 
Cc: Carlo Caione 
Cc: Dinh Nguyen 
Link: http://lkml.kernel.org/r/1470045256-9032-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner