linux-stable.git/drivers/clk, branch v6.18.2

clk: keystone: fix compile testing

2025-12-18T13:03:28+00:00

[ Upstream commit b276445e98fe28609688fb85b89a81b803910e63 ]

Some keystone clock drivers can be selected when COMPILE_TEST is
enabled but since commit b745c0794e2f ("clk: keystone: Add sci-clk
driver support") they are never actually built.

Enable compile testing by allowing the build system to process the
keystone drivers.

Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support")
Signed-off-by: Johan Hovold 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: spacemit: Set clk_hw_onecell_data::num before using flex array

2025-12-18T13:03:09+00:00

[ Upstream commit 23b2d2fb136959fd0a8e309c70be83d9b8841c7e ]

When booting with KASAN enabled the following splat is
encountered during probe of the k1 clock driver:

UBSAN: array-index-out-of-bounds in drivers/clk/spacemit/ccu-k1.c:1044:16
index 0 is out of range for type 'clk_hw *[*]'
CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.18.0-rc5+ #1 PREEMPT(lazy)
Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2022.10spacemit 10/01/2022
Call Trace:
[] dump_backtrace+0x28/0x38
[] show_stack+0x3a/0x50
[] dump_stack_lvl+0x5a/0x80
[] dump_stack+0x18/0x20
[] ubsan_epilogue+0x10/0x48
[] __ubsan_handle_out_of_bounds+0xa6/0xa8
[] k1_ccu_probe+0x37e/0x420
[] platform_probe+0x56/0x98
[] really_probe+0x9e/0x350
[] __driver_probe_device+0x80/0x138
[] driver_probe_device+0x3a/0xd0
[] __driver_attach+0xac/0x1b8
[] bus_for_each_dev+0x6c/0xc8
[] driver_attach+0x26/0x38
[] bus_add_driver+0x13e/0x268
[] driver_register+0x52/0x100
[] __platform_driver_register+0x28/0x38
[] k1_ccu_driver_init+0x22/0x38
[] do_one_initcall+0x62/0x2a0
[] do_initcalls+0x170/0x1a8
[] kernel_init_freeable+0x16a/0x1e0
[] kernel_init+0x2c/0x180
[] ret_from_fork_kernel+0x16/0x1d8
[] ret_from_fork_kernel_asm+0x16/0x18
---[ end trace ]---

This is bogus and is simply a result of KASAN consulting the
`.num` member of the struct for bounds information (as it should
due to `__counted_by`) and finding 0 set by kzalloc() because it
has not been initialized before the loop that fills in the array.
The easy fix is to just move the line that sets `num` to before
the loop that fills the array so that KASAN has the information
it needs to accurately conclude that the access is valid.

Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Tested-by: Yanko Kaneti 
Signed-off-by: Charles Mirabile 
Reviewed-by: Alex Elder 
Reviewed-by: Troy Mitchell 
Reviewed-by: Yixun Lan 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: renesas: r9a06g032: Fix memory leak in error path

2025-12-18T13:02:57+00:00

[ Upstream commit f8def051bbcf8677f64701e9699bf6d11e2780cd ]

The current code uses of_iomap() to map registers but never calls
iounmap() on any error path after the mapping. This causes a memory
leak when probe fails after successful ioremap, for example when
of_clk_add_provider() or r9a06g032_add_clk_domain() fails.

Replace of_iomap() with devm_of_iomap() to automatically unmap the
region on probe failure. Update the error check accordingly to use
IS_ERR() and PTR_ERR() since devm_of_iomap() returns ERR_PTR on error.

Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: Haotian Zhang 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20251030061603.1954-1-vulab@iscas.ac.cn
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Sasha Levin

clk: renesas: r9a09g077: Propagate rate changes to parent clocks

2025-12-18T13:02:57+00:00

[ Upstream commit 145dfd70b9c70e5bc03494a7ce8fa3748ac01af3 ]

Add the CLK_SET_RATE_PARENT flag to divider clock registration so that rate
changes can propagate to parent clocks when needed. This allows the CPG
divider clocks to request rate adjustments from their parent, ensuring
correct frequency scaling and improved flexibility in clock rate selection.

Fixes: 065fe720eec6e ("clk: renesas: Add support for R9A09G077 SoC")
Signed-off-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://patch.msgid.link/20251028165127.991351-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Sasha Levin

clk: qcom: tcsrcc-glymur: Update register offsets for clock refs

2025-12-18T13:02:46+00:00

[ Upstream commit a4aa1ceb89f5c0d27a55671d88699cf5eae7331b ]

Update the register offsets for all the clock ref branches to match the
new address mapping in the TCSR subsystem.

Fixes: 2c1d6ce4f3da ("clk: qcom: Add TCSR clock driver for Glymur SoC")
Signed-off-by: Taniya Das 
Reviewed-by: Abel Vesa 
Tested-by: Jagadeesh Kona 
Link: https://lore.kernel.org/r/20251031-tcsrcc_glymur-v1-1-0efb031f0ac5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson 
Signed-off-by: Sasha Levin

clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops

2025-12-18T13:02:43+00:00

[ Upstream commit 0820c9373369c83de5202871d02682d583a91a9c ]

Fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" during
boot. This happens due to the floor_ops tries to update the rcg
configuration even if the clock is not enabled.
The shared_floor_ops ensures that the RCG is safely parked and the new
parent configuration is cached in the parked_cfg when the clock is off.

Ensure to use the ops for the other SDCC clock instances as well.

Fixes: 39d6dcf67fe9 ("clk: qcom: gcc: Add support for QCS615 GCC clocks")
Reviewed-by: Abel Vesa 
Signed-off-by: Taniya Das 
Reviewed-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20251029-sdcc_rcg2_shared_ops-v3-1-ecf47d9601d1@oss.qualcomm.com
Signed-off-by: Bjorn Andersson 
Signed-off-by: Sasha Levin

clk: qcom: camcc-sm7150: Fix PLL config of PLL2

2025-12-18T13:02:35+00:00

[ Upstream commit 415aad75c7e5cdb72e0672dc1159be1a99535ecd ]

The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
parameters that are provided in the vendor driver. Instead the upstream
configuration should provide the final user_ctl value that is written to
the USER_CTL register.

Fix the config so that the PLL is configured correctly.

Fixes: 9f0532da4226 ("clk: qcom: Add Camera Clock Controller driver for SM7150")
Suggested-by: Taniya Das 
Signed-off-by: Luca Weiss 
Reviewed-by: Abel Vesa 
Reviewed-by: Taniya Das 
Link: https://lore.kernel.org/r/20251021-agera-pll-fixups-v1-2-8c1d8aff4afc@fairphone.com
Signed-off-by: Bjorn Andersson 
Signed-off-by: Sasha Levin

clk: qcom: camcc-sm6350: Fix PLL config of PLL2

2025-12-18T13:02:35+00:00

[ Upstream commit ab0e13141d679fdffdd3463a272c5c1b10be1794 ]

The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
parameters that are provided in the vendor driver. Instead the upstream
configuration should provide the final user_ctl value that is written to
the USER_CTL register.

Fix the config so that the PLL is configured correctly, and fixes
CAMCC_MCLK* being stuck off.

Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
Suggested-by: Taniya Das 
Signed-off-by: Luca Weiss 
Reviewed-by: Abel Vesa 
Reviewed-by: Taniya Das 
Link: https://lore.kernel.org/r/20251021-agera-pll-fixups-v1-1-8c1d8aff4afc@fairphone.com
Signed-off-by: Bjorn Andersson 
Signed-off-by: Sasha Levin

clk: qcom: gcc-ipq5424: Correct the icc_first_node_id

2025-12-18T13:02:35+00:00

[ Upstream commit 464ce94531f5a62ce29081a9d3c70eb4d525f443 ]

Update to use the expected icc_first_node_id for registering the icc
clocks, ensuring correct association of clocks with interconnect nodes.

Fixes: 170f3d2c065e ("clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks")
Reviewed-by: Konrad Dybcio 
Signed-off-by: Luo Jie 
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-1-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson 
Signed-off-by: Sasha Levin

clk: qcom: gcc-glymur: Update the halt check flags for pipe clocks

2025-12-18T13:02:35+00:00

[ Upstream commit 18da820eb632fbd99167f3fc6650a30db714ddfd ]

The pipe clocks for PCIE and USB are externally sourced and they should
not be polled by the clock driver. Update the halt_check flags to 'SKIP'
to disable polling for these clocks.

This helps avoid the clock status stuck at 'off' warnings, which are
benign, since all consumers of the PHYs must initialize a given instance
before performing any operations.

Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller")
Reviewed-by: Konrad Dybcio 
Signed-off-by: Taniya Das 
Reviewed-by: Imran Shaik 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20250925-glymur_gcc_usb_fixes-v2-1-ee4619571efe@oss.qualcomm.com
Signed-off-by: Bjorn Andersson 
Signed-off-by: Sasha Levin