While the user manual states that the PLL's rate should be between 180
MHz and 3 GHz in the register defninition section, it also says the
actual operating frequency is 22.5792*4 MHz in the PLL features table.
22.5792*4 MHz is one of the actual clock rates that we want and is
is available in the SDM table. Lower the minimum clock rate to 90 MHz
so that both rates in the SDM table can be used.
Fixes: 7cae1e2b5544 ("clk: sunxi-ng: Add support for the A523/T527 CCU PLLs")
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251020171059.2786070-7-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
The "bus-r-dma" clock in the A523's PRCM clock controller is also
referred to as "DMA_CLKEN_SW" or "DMA ADB400 gating". It is unclear how
this ties into the DMA controller MBUS clock gate; however if the clock
is not enabled, the DMA controller in the MCU block will fail to access
DRAM, even failing to retrieve the DMA descriptors.
Mark this clock as critical. This sort of mirrors what is done for the
main DMA controller's MBUS clock, which has a separate toggle that is
currently left out of the main clock controller driver.
Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251020171059.2786070-6-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
bus-r-cpucfg clock is important for peripheral which takes care of
powering CPU cores on and off. Since this operation is done by firmware
(TF-A), mark it as critical. That way Linux won't interfere with that
clock.
Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20251020152704.4804-1-jernej.skrabec@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Pull clk updates from Stephen Boyd: "There's a bunch of patches here across drivers/clk/ to migrate drivers to use struct clk_ops::determine_rate() instead of the round_rate() one so that we can remove the round_rate clk_op entirely. Brian has taken up that task which nobody else has wanted to do for close to a decade. Thanks Brian! This is all prerequisite work to get to the real task of improving the clk rate setting process. Once we have determine_rate() used everywhere, we'll be able to do things like chain the rate request structs in linked lists to order the rate setting operations or add more parameters without having to change every clk driver in existence. It's also nice to not have multiple ways to do something which just causes confusion for clk driver authors. Overall I'm glad this is getting done. Beyond this change we also have a tweak to the clk_lookup() function in the core framework to use hashing on the clk name instead of a clk tree walk with string comparisons. We _still_ rely on the clk name to be unique, because historically we've used globally unique strings to describe the clk tree topology. This tree walk becomes increasingly slow as more clks are added to the system. Searching from the roots for a duplicate is simple but pretty dumb and it wastes boot time so we're using a hash table as an improvement. Ideally we wouldn't rely on the strings to be unique at all, relegating them to simply debug information, but that is future work that will likely require some sort of Kconfig knob indicating strings aren't used for topology description. Outside of the core framework changes we have the usual new SoC support and fixes to clk drivers for things that were discovered once the clks were used by consumer drivers. Nothing in particular is jumping out at me in the "misc" pile, except maybe the Amlogic driver that has gone through a refactoring. That series got a fix from testing in -next though so it seems likely that things have been getting good test coverage for a couple weeks already" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits) clk: microchip: core: remove duplicate roclk_determine_rate() reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() clk: mmp: pxa1908: Instantiate power driver through auxiliary bus clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings ...
* clk-determine-rate: (120 commits) clk: microchip: core: remove duplicate roclk_determine_rate() clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: scmi: migrate round_rate() to determine_rate() clk: ti: fapll: convert from round_rate() to determine_rate() clk: ti: dra7-atl: convert from round_rate() to determine_rate() clk: ti: divider: convert from round_rate() to determine_rate() clk: ti: composite: convert from round_rate() to determine_rate() clk: ti: dpll: convert from round_rate() to determine_rate() clk: ti: dpll: change error return from ~0 to -EINVAL clk: ti: dpll: remove round_rate() in favor of determine_rate() clk: tegra: tegra210-emc: convert from round_rate() to determine_rate() clk: tegra: super: convert from round_rate() to determine_rate() clk: tegra: pll: convert from round_rate() to determine_rate() clk: tegra: periph: divider: convert from round_rate() to determine_rate() clk: tegra: divider: convert from round_rate() to determine_rate() clk: tegra: audio-sync: convert from round_rate() to determine_rate() clk: fixed-factor: drop round_rate() clk ops clk: divider: remove round_rate() in favor of determine_rate() clk: visconti: pll: convert from round_rate() to determine_rate() clk: versatile: vexpress-osc: convert from round_rate() to determine_rate() ...
* clk-aspeed: reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define * clk-rockchip: clk: rockchip: rk3368: use clock ids for SCLK_MIPIDSI_24M dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
- Add Mediatek MT8196 clk drivers * clk-marvell: clk: mmp: pxa1908: Instantiate power driver through auxiliary bus * clk-xilinx: clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() * clk-mediatek: (31 commits) clk: mediatek: Add MT8196 vencsys clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 apmixedsys clock support dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro ... * clk-loongson: clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
- Speed up clk_core_lookup() by using a hashtable * clk-microchip: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable * clk-lookup: clk: Use hashtable for global clk lookups clk: Sort include statements * clk-st: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings
* clk-scmi: clk: scmi: Add duty cycle ops only when duty cycle is supported * clk-qcom: (27 commits) clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller clk: qcom: Select the intended config in QCS_DISPCC_615 clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register() clk: qcom: alpha-pll: convert from round_rate() to determine_rate() clk: qcom: milos: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock Controller dt-bindings: clock: qcom: document the Glymur Global Clock Controller clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL clk: qcom: rpmh: Add support for Glymur rpmh clocks clk: qcom: Add TCSR clock driver for Glymur SoC dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs clk: qcom: dispcc-glymur: Add support for Display Clock Controller dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs ... * clk-broadcom: clk: bcm: rpi: Maximize V3D clock clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing clk: bcm: rpi: Add missing logs if firmware fails
* clk-imx: clk: imx95-blk-ctl: Save/restore registers when RPM routines are called clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure * clk-allwinner: clk: sunxi-ng: add support for the A523/T527 MCU CCU clk: sunxi-ng: div: support power-of-two dividers clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock clk: sunxi-ng: sun6i-rtc: Add A523 specifics * clk-ti: clk: keystone: sci-clk: use devm_kmemdup_array() clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled