linux-stable.git/drivers/clk, branch v5.4.97

clk: tegra30: Add hda clock default rates to clock driver

2021-01-27T10:47:44+00:00

[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]

Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.

This matches upstream t124 and downstream t30.

Acked-by: Jon Hunter 
Tested-by: Ion Agorria 
Acked-by: Sameer Pujar 
Acked-by: Thierry Reding 
Signed-off-by: Peter Geis 
Link: https://lore.kernel.org/r/20210108135913.2421585-2-pgwipeout@gmail.com
Signed-off-by: Takashi Iwai 
Signed-off-by: Sasha Levin

clk: tegra: Do not return 0 on failure

2020-12-30T10:51:46+00:00

commit 6160aca443148416994c022a35c77daeba948ea6 upstream.

Return values from read_dt_param() will be either TRUE (1) or
FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
or an ERR code on failure.

So this patch fixes the bug of returning 0 on failure.

Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
Cc: 
Signed-off-by: Nicolin Chen 
Signed-off-by: Thierry Reding 
Signed-off-by: Greg Kroah-Hartman

clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9

2020-12-30T10:51:45+00:00

commit 6f37689cf6b38fff96de52e7f0d3e78f22803ba0 upstream.

There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: Terry Zhou 
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár 
Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: ingenic: Fix divider calculation with div tables

2020-12-30T10:51:45+00:00

commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream.

The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.

Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.

Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
Cc:  # 5.2
Signed-off-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: Make sure divider tables have sentinel

2020-12-30T10:51:29+00:00

[ Upstream commit 48f68de00c1405351fa0e7bc44bca067c49cd0a3 ]

Two clock divider tables are missing sentinel at the end. Effect of that
is that clock framework reads past the last entry. Fix that with adding
sentinel at the end.

Issue was discovered with KASan.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Jernej Skrabec 
Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.net
Acked-by: Maxime Ripard 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: s2mps11: Fix a resource leak in error handling paths in the probe function

2020-12-30T10:51:29+00:00

[ Upstream commit d2d94fc567624f96187e8b52083795620f93e69f ]

Some resource should be released in the error handling path of the probe
function, as already done in the remove function.

The remove function was fixed in commit bf416bd45738 ("clk: s2mps11: Add
missing of_node_put and of_clk_del_provider")

Fixes: 7cc560dea415 ("clk: s2mps11: Add support for s2mps11")
Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/20201212122818.86195-1-christophe.jaillet@wanadoo.fr
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: at91: sam9x60: remove atmel,osc-bypass support

2020-12-30T10:51:29+00:00

[ Upstream commit 01324f9e88b5cfc1f4c26eef66bdcb52596c9af8 ]

The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
bypass.

Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Reported-by: Claudiu Beznea 
Signed-off-by: Alexandre Belloni 
Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com
Reviewed-by: Claudiu Beznea 
Tested-by: Claudiu Beznea 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: ti: Fix memleak in ti_fapll_synth_setup

2020-12-30T10:51:28+00:00

[ Upstream commit 8c6239f6e95f583bb763d0228e02d4dd0fb3d492 ]

If clk_register fails, we should goto free branch
before function returns to prevent memleak.

Fixes: 163152cbbe321 ("clk: ti: Add support for FAPLL on dm816x")
Reported-by: Hulk Robot 
Signed-off-by: Zhang Qilong 
Link: https://lore.kernel.org/r/20201113131623.2098222-1-zhangqilong3@huawei.com
Acked-by: Tony Lindgren 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: tegra: Fix duplicated SE clock entry

2020-12-30T10:51:24+00:00

[ Upstream commit 5bf5861d6ea6c3f4b38fc8fda2062b2dc44ac63d ]

The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".

Fixes: dc37fec48314 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet 
Reported-by Nicolas Chauvet 
Signed-off-by: Dmitry Osipenko 
Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com
Acked-by: Thierry Reding 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: meson: Kconfig: fix dependency for G12A

2020-12-30T10:51:11+00:00

[ Upstream commit bae69bfa3a586493469078ec4ca35499b754ba5c ]

When building only G12A, ensure that VID_PLL_DIV clock driver is
selected, otherwise results in this build error:

ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined!

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Kevin Hilman 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20201118190930.34352-1-khilman@baylibre.com
Signed-off-by: Sasha Levin