linux-stable.git/drivers/clk, branch v5.4.78

clk: ti: clockdomain: fix static checker warning

2020-11-05T10:43:20+00:00

[ Upstream commit b7a7943fe291b983b104bcbd2f16e8e896f56590 ]

Fix a memory leak induced by not calling clk_put after doing of_clk_get.

Reported-by: Dan Murphy 
Signed-off-by: Tero Kristo 
Link: https://lore.kernel.org/r/20200907082600.454-3-t-kristo@ti.com
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: imx8mq: Fix usdhc parents order

2020-10-29T08:57:56+00:00

[ Upstream commit b159c63d82ff8ffddc6c6f0eb881b113b36ecad7 ]

According to the latest RM (see Table 5-1. Clock Root Table),
both usdhc root clocks have the parent order as follows:

000 - 25M_REF_CLK
001 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
101 - SYSTEM_PLL1_DIV3
110 - AUDIO_PLL2_CLK
111 - SYSTEM_PLL1_DIV8

So the audio_pll2_out and sys3_pll_out have to be swapped.

Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa 
Reported-by: Cosmin Stefan Stoica 
Link: https://lore.kernel.org/r/1602753944-30757-1-git-send-email-abel.vesa@nxp.com
Reviewed-by: Fabio Estevam 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: bcm2835: add missing release if devm_clk_hw_register fails

2020-10-29T08:57:55+00:00

[ Upstream commit f6c992ca7dd4f49042eec61f3fb426c94d901675 ]

In the implementation of bcm2835_register_pll(), the allocated pll is
leaked if devm_clk_hw_register() fails to register hw. Release pll if
devm_clk_hw_register() fails.

Signed-off-by: Navid Emamdoost 
Link: https://lore.kernel.org/r/20200809231202.15811-1-navid.emamdoost@gmail.com
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: at91: clk-main: update key before writing AT91_CKGR_MOR

2020-10-29T08:57:55+00:00

[ Upstream commit 85d071e7f19a6a9abf30476b90b3819642568756 ]

SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
Main Oscillator Register) that writing any value other than
0x37 on KEY field aborts the write operation. Use the key when
selecting main clock parent.

Fixes: 27cb1c2083373 ("clk: at91: rework main clk implementation")
Signed-off-by: Claudiu Beznea 
Reviewed-by: Alexandre Belloni 
Link: https://lore.kernel.org/r/1598338751-20607-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: mediatek: add UART0 clock support

2020-10-29T08:57:54+00:00

[ Upstream commit 804a892456b73604b7ecfb1b00a96a29f3d2aedf ]

Add MT6779 UART0 clock support.

Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin 
Signed-off-by: Hanks Chen 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: rockchip: Initialize hw to error to avoid undefined behavior

2020-10-29T08:57:54+00:00

[ Upstream commit b608f11d49ec671739604cc763248d8e8fadbbeb ]

We can get down to this return value from ERR_CAST() without
initializing hw. Set it to -ENOMEM so that we always return something
sane.

Fixes the following smatch warning:

drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'.
drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST'

Cc: Elaine Zhang 
Cc: Heiko Stuebner 
Fixes: 956060a52795 ("clk: rockchip: add support for half divider")
Reviewed-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: keystone: sci-clk: fix parsing assigned-clock data during probe

2020-10-29T08:57:54+00:00

[ Upstream commit 2f05cced7307489faab873367fb20cd212e1d890 ]

The DT clock probe loop incorrectly terminates after processing "clocks"
only, fix this by re-starting the loop when all entries for current
DT property have been parsed.

Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware")
Reported-by: Peter Ujfalusi 
Signed-off-by: Tero Kristo 
Link: https://lore.kernel.org/r/20200907085740.1083-2-t-kristo@ti.com
Acked-by: Santosh Shilimkar 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: gcc-sdm660: Fix wrong parent_map

2020-10-29T08:57:54+00:00

[ Upstream commit d46e5a39f9be9288f1ce2170c4c7f8098f4e7f68 ]

This was likely overlooked while porting the driver upstream.

Reported-by: Pavel Dubrova 
Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20200922120909.97203-1-konradybcio@gmail.com
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: meson: g12a: mark fclk_div2 as critical

2020-10-29T08:57:53+00:00

[ Upstream commit 2c4e80e06790cb49ad2603855d30c5aac2209c47 ]

On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2
seems to be necessary for the system to operate correctly as well.

Typically, the clock also gets chosen by the eMMC peripheral. This
probably masked the problem so far. However, when booting from a SD
card the clock seems to get disabled which leads to a system freeze.

Let's mark this clock as critical, fixing boot from SD card on G12b
platforms.

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Stefan Agner 
Signed-off-by: Jerome Brunet 
Tested-by: Anand Moon 
Cc: Marek Szyprowski 
Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch
Signed-off-by: Sasha Levin

clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED

2020-10-07T06:01:28+00:00

[ Upstream commit f3bb0f796f5ffe32f0fbdce5b1b12eb85511158f ]

The ChipID IO region has it's own clock, which is being disabled while
scanning for unused clocks. It turned out that some CPU hotplug, CPU idle
or even SOC firmware code depends on the reads from that area. Fix the
mysterious hang caused by entering deep CPU idle state by ignoring the
'chipid' clock during unused clocks scan, as there are no direct clients
for it which will keep it enabled.

Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework")
Signed-off-by: Marek Szyprowski 
Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Sylwester Nawrocki 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin