linux-stable.git/drivers/clk, branch v5.4.71

clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED

2020-10-07T06:01:28+00:00

[ Upstream commit f3bb0f796f5ffe32f0fbdce5b1b12eb85511158f ]

The ChipID IO region has it's own clock, which is being disabled while
scanning for unused clocks. It turned out that some CPU hotplug, CPU idle
or even SOC firmware code depends on the reads from that area. Fix the
mysterious hang caused by entering deep CPU idle state by ignoring the
'chipid' clock during unused clocks scan, as there are no direct clients
for it which will keep it enabled.

Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework")
Signed-off-by: Marek Szyprowski 
Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com
Reviewed-by: Krzysztof Kozlowski 
Acked-by: Sylwester Nawrocki 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: tegra: Always program PLL_E when enabled

2020-10-07T06:01:28+00:00

[ Upstream commit 5105660ee80862b85f7769626d0f936c18ce1885 ]

Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
added checks to avoid enabling PLLs that have already been enabled by
the bootloader. However, the PLL_E configuration inherited from the
bootloader isn't necessarily the one that is needed for the kernel.

This can cause SATA to fail like this:

    [    5.310270] phy phy-sata.6: phy poweron failed --> -110
    [    5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110
    [    5.323022] tegra-ahci: probe of 70027000.sata failed with error -110

Fix this by always programming the PLL_E. This ensures that any mis-
configuration by the bootloader will be overwritten by the kernel.

Fixes: bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs")
Reported-by: LABBE Corentin 
Tested-by: Corentin Labbe 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk

2020-10-07T06:01:24+00:00

commit b02cf0c4736c65c6667f396efaae6b5521e82abf upstream.

The fixed divider the emac_ptp_free_clk should be 2, not 4.

Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen 
Link: https://lore.kernel.org/r/20200831202657.8224-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: imx: Fix division by zero warning on pfdv2

2020-10-01T11:17:40+00:00

[ Upstream commit 28b2f82e0383e27476be8a5e13d2aea07ebeb275 ]

Fix below division by zero warning:

[    3.176443] Division by zero in kernel.
[    3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124
[    3.191817] Hardware name: Freescale i.MX7ULP (Device Tree)
[    3.197821] Workqueue: events dbs_work_handler
[    3.202849] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    3.211058] [] (show_stack) from [] (dump_stack+0xd8/0x110)
[    3.218820] [] (dump_stack) from [] (Ldiv0_64+0x8/0x18)
[    3.226263] [] (Ldiv0_64) from [] (clk_pfdv2_set_rate+0x54/0xac)
[    3.234487] [] (clk_pfdv2_set_rate) from [] (clk_change_rate+0x1a4/0x698)
[    3.243468] [] (clk_change_rate) from [] (clk_change_rate+0x280/0x698)
[    3.252180] [] (clk_change_rate) from [] (clk_core_set_rate_nolock+0x1a0/0x278)
[    3.261679] [] (clk_core_set_rate_nolock) from [] (clk_set_rate+0x30/0x64)
[    3.270743] [] (clk_set_rate) from [] (imx7ulp_set_target+0x184/0x2a4)
[    3.279501] [] (imx7ulp_set_target) from [] (__cpufreq_driver_target+0x188/0x514)
[    3.289196] [] (__cpufreq_driver_target) from [] (od_dbs_update+0x130/0x15c)
[    3.298438] [] (od_dbs_update) from [] (dbs_work_handler+0x2c/0x5c)
[    3.306914] [] (dbs_work_handler) from [] (process_one_work+0x2ac/0x704)
[    3.315826] [] (process_one_work) from [] (worker_thread+0x2c/0x574)
[    3.324404] [] (worker_thread) from [] (kthread+0x134/0x148)
[    3.332278] [] (kthread) from [] (ret_from_fork+0x14/0x20)
[    3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8)
[    3.345314] 5fa0:                                     00000000 00000000 00000000 00000000
[    3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[    3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000

Signed-off-by: Anson Huang 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo 
Signed-off-by: Sasha Levin

clk: stratix10: use do_div() for 64-bit calculation

2020-10-01T11:17:33+00:00

[ Upstream commit cc26ed7be46c5f5fa45f3df8161ed7ca3c4d318c ]

do_div() macro to perform u64 division and guards against overflow if
the result is too large for the unsigned long return type.

Signed-off-by: Dinh Nguyen 
Link: https://lkml.kernel.org/r/20200114160726.19771-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk/ti/adpll: allocate room for terminating null

2020-10-01T11:17:16+00:00

[ Upstream commit 7f6ac72946b88b89ee44c1c527aa8591ac5ffcbe ]

The buffer allocated in ti_adpll_clk_get_name doesn't account for the
terminating null. This patch switches to devm_kasprintf to avoid
overflowing.

Signed-off-by: Stephen Kitt 
Link: https://lkml.kernel.org/r/20191019140634.15596-1-steve@sk2.org
Acked-by: Tony Lindgren 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: rockchip: Fix initialization of mux_pll_src_4plls_p

2020-09-23T10:40:39+00:00

[ Upstream commit e9c006bc782c488f485ffe50de20b44e1e3daa18 ]

A new warning in Clang points out that the initialization of
mux_pll_src_4plls_p appears incorrect:

../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious
concatenation of string literals in an array initialization; did you
mean to separate the elements with a comma? [-Wstring-concatenation]
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                              ^
                                                             ,
../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses
around the string literal to silence warning
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                    ^
1 warning generated.

Given the name of the variable and the same variable name in rv1108, it
seems that this should have been four distinct elements. Fix it up by
adding the comma as suggested.

Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Link: https://github.com/ClangBuiltLinux/linux/issues/1123
Signed-off-by: Nathan Chancellor 
Link: https://lore.kernel.org/r/20200810044020.2063350-1-natechancellor@gmail.com
Reviewed-by: Heiko Stübner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: davinci: Use the correct size when allocating memory

2020-09-23T10:40:38+00:00

[ Upstream commit 3dabfa2bda48dab717986609762ce2a49335eb99 ]

'sizeof(*pllen)' should be used in place of 'sizeof(*pllout)' to avoid a
small over-allocation.

Fixes: 2d1726915159 ("clk: davinci: New driver for davinci PLL clocks")
Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/20200809144959.747986-1-christophe.jaillet@wanadoo.fr
Reviewed-by: David Lechner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: bcm2835: Do not use prediv with bcm2711's PLLs

2020-08-21T11:05:35+00:00

[ Upstream commit f34e4651ce66a754f41203284acf09b28b9dd955 ]

Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL
feedback loop. Bypass it by zeroing fb_prediv_mask when running on
bcm2711.

Note that, since the prediv configuration bits were re-purposed, this
was triggering miscalculations on all clocks hanging from the VPU clock,
notably the aux UART, making its output unintelligible.

Fixes: 42de9ad400af ("clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support")
Reported-by: Nathan Chancellor 
Signed-off-by: Nicolas Saenz Julienne 
Link: https://lore.kernel.org/r/20200730182619.23246-1-nsaenzjulienne@suse.de
Tested-by: Nathan Chancellor 
Reviewed-by: Florian Fainelli 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: clk-atlas6: fix return value check in atlas6_clk_init()

2020-08-21T11:05:34+00:00

[ Upstream commit 12b90b40854a8461a02ef19f6f4474cc88d64b66 ]

In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().

Signed-off-by: Xu Wang 
Link: https://lore.kernel.org/r/20200713032143.21362-1-vulab@iscas.ac.cn
Acked-by: Barry Song 
Fixes: 7bf21bc81f28 ("clk: sirf: re-arch to make the codes support both prima2 and atlas6")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin