linux-stable.git/drivers/clk, branch v5.1.5

clk: rockchip: fix wrong clock definitions for rk3328

2019-05-25T16:16:33+00:00

commit fb903392131a324a243c7731389277db1cd9f8df upstream.

This patch fixes definition of several clock gate and select register
that is wrong for rk3328 referring to the TRM and vendor kernel.
Also use correct number of softrst registers.

Fix clock definition for:
- clk_crypto
- aclk_h265
- pclk_h265
- aclk_h264
- hclk_h264
- aclk_axisram
- aclk_gmac
- aclk_usb3otg

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: Jonas Karlman 
Tested-by: Peter Geis 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: mediatek: Disable tuner_en before change PLL rate

2019-05-25T16:16:32+00:00

commit be17ca6ac76a5cfd07cc3a0397dd05d6929fcbbb upstream.

PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.

Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
Cc: 
Signed-off-by: Owen Chen 
Signed-off-by: Weiyi Lu 
Reviewed-by: James Liao 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider

2019-05-25T16:16:32+00:00

commit 40db569d6769ffa3864fd1b89616b1a7323568a8 upstream.

There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.

Cc: 
Tested-by: Steev Klimaszewski 
Signed-off-by: Dmitry Osipenko 
Acked-By: Peter De Schrijver 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: hi3660: Mark clk_gate_ufs_subsys as critical

2019-05-25T16:16:32+00:00

commit 9f77a60669d13ed4ddfa6cd7374c9d88da378ffa upstream.

clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow.  Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.

Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: stable@vger.kernel.org
Cc: Zhong Kaihua 
Cc: John Stultz 
Cc: Zhangfei Gao 
Suggested-by: Dong Zhang 
Signed-off-by: Leo Yan 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'clk-fixes-for-5.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

2019-04-19T20:06:58+00:00

Pull Allwinner clk fixes from Maxime Ripard:

 - Some fixes for odd cases of the NKMP clocks

* tag 'clk-fixes-for-5.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: nkmp: Explain why zero width check is needed
  clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)

clkdev: Hold clocks_mutex while iterating clocks list

2019-04-18T20:33:13+00:00

We recently introduced a change to support devm clk lookups. That change
introduced a code-path that used clk_find() without holding the
'clocks_mutex'. Unfortunately, clk_find() iterates over the 'clocks'
list and so we need to prevent the list from being modified at the same
time. Do this by holding the mutex and checking to make sure it's held
while iterating the list.

Note, we don't really care if the lookup is freed after we find it with
clk_find() because we're just doing a pointer comparison, but if we did
care we would need to keep holding the mutex while we dereference the
clk_lookup pointer.

Fixes: 3eee6c7d119c ("clkdev: add managed clkdev lookup registration")
Cc: Miquel Raynal 
Cc: Jerome Brunet 
Cc: Russell King 
Cc: Michael Turquette 
Cc: Jeffrey Hugo 
Cc: Chen-Yu Tsai 
Cc: Matti Vaittinen 
Acked-by: Matti Vaittinen 
Tested-by: Jeffrey Hugo 
Signed-off-by: Stephen Boyd

clk: imx: Fix PLL_1416X not rounding rates

2019-04-12T21:21:43+00:00

Code which initializes the "clk_init_data.ops" checks pll->rate_table
before that field is ever assigned to so it always picks
"clk_pll1416x_min_ops".

This breaks dynamic rate rounding for features such as cpufreq.

Fix by checking pll_clk->rate_table instead, here pll_clk refers to
the constant initialization data coming from per-soc clk driver.

Signed-off-by: Leonard Crestez 
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Signed-off-by: Stephen Boyd

clk: mediatek: fix clk-gate flag setting

2019-04-12T16:41:49+00:00

CLK_SET_RATE_PARENT would be dropped.
Merge two flag setting together to correct the error.

Fixes: 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate")
Cc: 
Signed-off-by: Weiyi Lu 
Reviewed-by: Matthias Brugger 
Signed-off-by: Stephen Boyd

clk: x86: Add system specific quirk to mark clocks as critical

2019-04-10T22:54:12+00:00

Since commit 648e921888ad ("clk: x86: Stop marking clocks as
CLK_IS_CRITICAL"), the pmc_plt_clocks of the Bay Trail SoC are
unconditionally gated off. Unfortunately this will break systems where these
clocks are used for external purposes beyond the kernel's knowledge. Fix it
by implementing a system specific quirk to mark the necessary pmc_plt_clks as
critical.

Fixes: 648e921888ad ("clk: x86: Stop marking clocks as CLK_IS_CRITICAL")
Signed-off-by: David Müller 
Signed-off-by: Hans de Goede 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Stephen Boyd

clk: sunxi-ng: nkmp: Explain why zero width check is needed

2019-04-04T07:32:32+00:00

Add an explanation why zero width check is needed when generating factor
mask using GENMASK() macro.

Signed-off-by: Jernej Skrabec 
Signed-off-by: Maxime Ripard