linux-stable.git/drivers/clk, branch v4.9.64

clk: mvebu: adjust AP806 CPU clock frequencies to production chip

2017-11-15T14:53:16+00:00

[ Upstream commit 0c70ffc5f300e7c3a1a76ca0530860574afc890b ]

This commit adjusts the list of possible "Sample At Reset" values that
define the CPU clock frequency of the AP806 (part of Marvell Armada
7K/8K) to the values that have been validated with the production
chip. Earlier values were preliminary.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

2017-11-15T14:53:12+00:00

[ Upstream commit 5ccb58968bf7f46dbd128df88f71838a5a9750b8 ]

Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.

Signed-off-by: Marek Szyprowski 
Acked-by: Krzysztof Kozlowski 
Acked-by: Chanwoo Choi 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: Check kzalloc() for errors and cleanup error path

2017-11-08T09:08:35+00:00

[ Upstream commit 5d806f9fc8e63d7a44e0fd1ef26a7c27efae0e51 ]

This kzalloc() could fail. Let's bail out with -ENOMEM here
instead of NULL dereferencing. That silences static checkers. We
should also cleanup on the error path even though this function
returning an error probably means the system won't boot.

Cc: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk/axs10x: Clear init field in driver probe

2017-10-08T08:26:04+00:00

[ Upstream commit 6205406cf6f282d622f31de25036e6d1ab3a2ff5 ]

Init field must be cleared in driver probe as this structure is not
dinamically allocated. If not, wrong flags can be passed to core.

Signed-off-by: Jose Abreu 
Cc: Carlos Palminha 
Cc: Stephen Boyd 
Cc: Michael Turquette 
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver")
Signed-off-by: Michael Turquette 
Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: fix PLL_CPUX adjusting on H3

2017-10-08T08:26:02+00:00

[ Upstream commit a43c96427e713bea94e9ef50e8be1f493afc0691 ]

When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).

Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.

Signed-off-by: Ondrej Jirman 
Tested-by: Lutz Sammer 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk/samsung: exynos542x: mark some clocks as critical

2017-08-11T15:49:35+00:00

[ Upstream commit 318fa46cc60d37fec1e87dbf03a82aca0f5ce695 ]

Some parent clocks of the Exynos542x clock blocks, which have separate
power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always
enabled to access any register related to power management unit or devices
connected to it. For the time being, until a proper solution based on
runtime PM is applied, mark those clocks as critical (instead of ignore
unused or even no flags) to prevent disabling them.

Signed-off-by: Marek Szyprowski 
Acked-by: Sylwester Nawrocki 
Reviewed-by: Chanwoo Choi 
Reviewed-by: Javier Martinez Canillas 
Tested-by: Javier Martinez Canillas  [Exynos5800 Peach Pi Chromebook]
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: scpi: don't add cpufreq device if the scpi dvfs node is disabled

2017-07-05T12:40:30+00:00

commit 67bcc2c5f1da8c5bb58e72354274ea5c59a3950a upstream.

Currently we add the virtual cpufreq device unconditionally even when
the SCPI DVFS clock provider node is disabled. This will cause cpufreq
driver to throw errors when it gets initailised on boot/modprobe and
also when the CPUs are hot-plugged back in.

This patch fixes the issue by adding the virtual cpufreq device only if
the SCPI DVFS clock provider is available and registered.

Fixes: 9490f01e2471 ("clk: scpi: add support for cpufreq virtual device")
Reported-by: Michał Zegan 
Cc: Neil Armstrong 
Signed-off-by: Sudeep Holla 
Tested-by: Michał Zegan 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

2017-06-29T11:00:27+00:00

commit 38b8f823864707eb1cf331d2247608c419ed388c upstream.

The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: Bob Ham 
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

2017-05-14T12:00:19+00:00

commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28 upstream.

The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.

Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: Make x86/ conditional on CONFIG_COMMON_CLK

2017-05-14T12:00:17+00:00

commit f35b6542c3ac3f28056d298348a81f7d56d3a041 upstream.

Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK
was not explicit

Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks')
Signed-off-by: Pierre-Louis Bossart 
Acked-by: Andy Shevchenko 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman