linux-stable.git/drivers/clk, branch v4.9.183

clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288

2019-06-22T06:17:15+00:00

[ Upstream commit 57a20248ef3e429dc822f0774bc4e00136c46c83 ]

Experimentally it can be seen that going into deep sleep (specifically
setting PMU_CLR_DMA and PMU_CLR_BUS in RK3288_PMU_PWRMODE_CON1)
appears to fail unless "aclk_dmac1" is on.  The failure is that the
system never signals that it made it into suspend on the GLOBAL_PWROFF
pin and it just hangs.

NOTE that it's confirmed that it's the actual suspend that fails, not
one of the earlier calls to read/write registers.  Specifically if you
comment out the "PMU_GLOBAL_INT_DISABLE" setting in
rk3288_slp_mode_set() and then comment out the "cpu_do_idle()" call in
rockchip_lpmode_enter() then you can exercise the whole suspend path
without any crashing.

This is currently not a problem with suspend upstream because there is
no current way to exercise the deep suspend code.  However, anyone
trying to make it work will run into this issue.

This was not a problem on shipping rk3288-based Chromebooks because
those devices all ran on an old kernel based on 3.14.  On that kernel
"aclk_dmac1" appears to be left on all the time.

There are several ways to skin this problem.

A) We could add "aclk_dmac1" to the list of critical clocks and that
apperas to work, but presumably that wastes power.

B) We could keep a list of "struct clk" objects to enable at suspend
time in clk-rk3288.c and use the standard clock APIs.

C) We could make the rk3288-pmu driver keep a list of clocks to enable
at suspend time.  Presumably this would require a dts and bindings
change.

D) We could just whack the clock on in the existing syscore suspend
function where we whack a bunch of other clocks.  This is particularly
easy because we know for sure that the clock's only parent
("aclk_cpu") is a critical clock so we don't need to do anything more
than ungate it.

In this case I have chosen D) because it seemed like the least work,
but any of the other options would presumably also work fine.

Signed-off-by: Douglas Anderson 
Reviewed-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider

2019-05-25T16:26:48+00:00

commit 40db569d6769ffa3864fd1b89616b1a7323568a8 upstream.

There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.

Cc: 
Tested-by: Steev Klimaszewski 
Signed-off-by: Dmitry Osipenko 
Acked-By: Peter De Schrijver 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: ingenic: Fix doc of ingenic_cgu_div_info

2019-03-23T12:19:49+00:00

commit 7ca4c922aad2e3c46767a12f80d01c6b25337b59 upstream.

The 'div' field does not represent a number of bits used to divide
(understand: right-shift) the divider, but a number itself used to
divide the divider.

Signed-off-by: Paul Cercueil 
Signed-off-by: Maarten ter Huurne 
Cc: 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: ingenic: Fix round_rate misbehaving with non-integer dividers

2019-03-23T12:19:49+00:00

commit bc5d922c93491878c44c9216e9d227c7eeb81d7f upstream.

Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz.
This results in a theorical divider of 41.999993 which is then rounded
up to 42. The .round_rate function would then return (180 MHz / 42) as
the clock, rounded down, so 4.285714 MHz.

Calling clk_set_rate on 4.285714 MHz would round the rate again, and
give a theorical divider of 42,0000028, now rounded up to 43, and the
rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not
what we requested.

Fix this by rounding up the divisions.

Signed-off-by: Paul Cercueil 
Tested-by: Maarten ter Huurne 
Cc: 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: clk-twl6040: Fix imprecise external abort for pdmclk

2019-03-23T12:19:49+00:00

commit 5ae51d67aec95f6f9386aa8dd5db424964895575 upstream.

I noticed that modprobe clk-twl6040 can fail after a cold boot with:
abe_cm:clk:0010:0: failed to enable
...
Unhandled fault: imprecise external abort (0x1406) at 0xbe896b20

WARNING: CPU: 1 PID: 29 at drivers/clk/clk.c:828 clk_core_disable_lock+0x18/0x24
...
(clk_core_disable_lock) from [] (_disable_clocks+0x18/0x90)
(_disable_clocks) from [] (_idle+0x17c/0x244)
(_idle) from [] (omap_hwmod_idle+0x24/0x44)
(omap_hwmod_idle) from [] (sysc_runtime_suspend+0x48/0x108)
(sysc_runtime_suspend) from [] (__rpm_callback+0x144/0x1d8)
(__rpm_callback) from [] (rpm_callback+0x20/0x80)
(rpm_callback) from [] (rpm_suspend+0x120/0x694)
(rpm_suspend) from [] (__pm_runtime_idle+0x60/0x84)
(__pm_runtime_idle) from [] (sysc_probe+0x874/0xf2c)
(sysc_probe) from [] (platform_drv_probe+0x48/0x98)

After searching around for a similar issue, I came across an earlier fix
that never got merged upstream in the Android tree for glass-omap-xrr02.
There is patch "MFD: twl6040-codec: Implement PDMCLK cold temp errata"
by Misael Lopez Cruz .

Based on my observations, this fix is also needed when cold booting
devices, and not just for deeper idle modes. Since we now have a clock
driver for pdmclk, let's fix the issue in twl6040_pdmclk_prepare().

Cc: Misael Lopez Cruz 
Cc: Peter Ujfalusi 
Signed-off-by: Tony Lindgren 
Acked-by: Peter Ujfalusi 
Cc: 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi: A31: Fix wrong AHB gate number

2019-03-23T12:19:42+00:00

[ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin

clk: imx6sl: ensure MMDC CH0 handshake is bypassed

2019-02-12T18:44:54+00:00

[ Upstream commit 0efcc2c0fd2001a83240a8c3d71f67770484917e ]

Same as other i.MX6 SoCs, ensure unused MMDC channel's
handshake is bypassed, this is to make sure no request
signal will be generated when periphe_clk_sel is changed
or SRC warm reset is triggered.

Signed-off-by: Anson Huang 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks

2019-02-12T18:44:54+00:00

[ Upstream commit 6e6da2039c82271dd873b9ad2b902a692a7dd554 ]

All the audio interfaces on Allwinner SoCs need to change their module
clocks during operation, to switch between support for 44.1 kHz and 48
kHz family sample rates. The clock rate for the module clocks is
governed by their upstream audio PLL. The module clocks themselves only
have a gate, and sometimes a divider or mux. Thus any rate changes need
to be propagated upstream.

Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
this.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin

clk: imx6q: reset exclusive gates on init

2019-01-26T08:38:34+00:00

[ Upstream commit f7542d817733f461258fd3a47d77da35b2d9fc81 ]

The exclusive gates may be set up in the wrong way by software running
before the clock driver comes up. In that case the exclusive setup is
locked in its initial state, as the complementary function can't be
activated without disabling the initial setup first.

To avoid this lock situation, reset the exclusive gates to the off
state and allow the kernel to provide the proper setup.

Signed-off-by: Lucas Stach 
Reviewed-by: Dong Aisheng 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: rockchip: fix typo in rk3188 spdif_frac parent

2019-01-09T15:16:44+00:00

commit 8b19faf6fae2867e2c177212c541e8ae36aa4d32 upstream.

Fix typo in common_clk_branches.
Make spdif_pre parent of spdif_frac.

Fixes: 667464208989 ("clk: rockchip: include downstream muxes into fractional dividers")
Cc: stable@vger.kernel.org
Signed-off-by: Johan Jonker 
Acked-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman