linux-stable.git/drivers/clk, branch v4.5.2

clk: bcm2835: Fix setting of PLL divider clock rates

2016-04-12T14:33:46+00:00

commit 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 upstream.

Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Signed-off-by: Eric Anholt 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks

2016-04-12T14:33:46+00:00

commit e8b63288b37dbb8457b510c9d96f6006da4653f6 upstream.

hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix hdmi_cec gate-register

2016-04-12T14:33:46+00:00

commit fd0c0740fac17a014704ef89d8c8b1768711ca59 upstream.

Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix parents of video encoder/decoder

2016-04-12T14:33:46+00:00

commit 0f28d98463498c61c61a38aacbf9f69e92e85e9d upstream.

The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix cpuclk core dividers

2016-04-12T14:33:46+00:00

commit c6d5fe2ca8286f35a79f7345c9378c39d48a1527 upstream.

Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster

2016-04-12T14:33:46+00:00

commit 535ebd428aeb07c3327947281306f2943f2c9faa upstream.

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: ti: omap3+: dpll: use non-locking version of clk_get_rate

2016-02-22T22:03:02+00:00

As the code in this file is being executed within irq context in some
cases, we must avoid the clk_get_rate which uses mutex internally.
Switch the code to use clk_hw_get_rate instead which is non-locking.

This fixes an issue where PM runtime will hang the system if enabled
with a serial console before a suspend-resume cycle.

Signed-off-by: Tero Kristo 
Tested-by: Tony Lindgren 
Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs")
Signed-off-by: Stephen Boyd

clk: gpio: Really allow an optional clock= DT property

2016-02-19T03:10:22+00:00

We mis-merged the original patch from Russell here and so the
patch went almost all the way, except that we still failed to
probe when there wasn't a clocks property in the DT node. Allow
that case by making a negative value from
of_clk_get_parent_count() into "no parents", like the original
patch did.

Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property")
Cc: Russell King 
Cc: Michael Turquette 
Signed-off-by: Stephen Boyd

Revert "clk: qcom: Specify LE device endianness"

2016-02-12T22:24:24+00:00

This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87.

The commit that caused us to specify LE device endianness here,
29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.

Cc: Kevin Hilman 
Tested-by: Kevin Hilman 
Cc: Mark Brown 
Signed-off-by: Stephen Boyd

clk: versatile: mask VCO bits before writing

2016-02-10T17:56:31+00:00

The Versatile syscon ICST driver OR:s the bits into place but
forgets to mask the previous value, making the code only work
if the register is zero or giving haphazard results. Mask the
19 bits used by the Versatile syscon interface register.

Regression caused and now fixed by yours truly.

Cc: Michael Turquette 
Cc: Stephen Boyd 
Cc: linux-clk@vger.kernel.org
Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap")
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd