linux-stable.git/drivers/clk, branch v4.4.7

clk: bcm2835: Fix setting of PLL divider clock rates

2016-04-12T16:09:02+00:00

commit 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 upstream.

Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Signed-off-by: Eric Anholt 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks

2016-04-12T16:09:02+00:00

commit e8b63288b37dbb8457b510c9d96f6006da4653f6 upstream.

hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix hdmi_cec gate-register

2016-04-12T16:09:02+00:00

commit fd0c0740fac17a014704ef89d8c8b1768711ca59 upstream.

Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix parents of video encoder/decoder

2016-04-12T16:09:02+00:00

commit 0f28d98463498c61c61a38aacbf9f69e92e85e9d upstream.

The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix cpuclk core dividers

2016-04-12T16:09:02+00:00

commit c6d5fe2ca8286f35a79f7345c9378c39d48a1527 upstream.

Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster

2016-04-12T16:09:02+00:00

commit 535ebd428aeb07c3327947281306f2943f2c9faa upstream.

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Reviewed-by: zhangqing 
Signed-off-by: Greg Kroah-Hartman

clk: exynos: use irqsave version of spin_lock to avoid deadlock with irqs

2016-03-03T23:07:17+00:00

commit 6b4feaea251a97bf08c7d41eabdec07f63a11073 upstream.

It is allowed to enable/disable clocks from interrupts, so common Exynos
ARM clock management code for CPUfreq should use 'irqsave' version of
spin_lock calls to avoid potential deadlock caused by spin_lock recursion.
The same spin_lock is used by gate/mux clocks during enable/disable calls.

This deadlock, can be reproduced by enabling CPUfreq (ondemand or
userspace) and decoding video with s5p-mfc driver.

Relevant stack trace:
[ 5928.061534] BUG: spinlock recursion on CPU#0, bash/1252
[ 5928.061609]  lock: 0xee80454c, .magic: dead4ead, .owner: bash/1252, .owner_cpu: 0
[ 5928.068586] CPU: 0 PID: 1252 Comm: bash Tainted: G        W       4.4.0-rc4-00001-g447a7fd #678
[ 5928.077260] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[ 5928.083359] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[ 5928.091072] [] (show_stack) from [] (dump_stack+0x68/0xb8)
[ 5928.098275] [] (dump_stack) from [] (do_raw_spin_lock+0x184/0x1ac)
[ 5928.106177] [] (do_raw_spin_lock) from [] (_raw_spin_lock_irqsave+0x20/0x28)
[ 5928.114943] [] (_raw_spin_lock_irqsave) from [] (clk_gate_endisable+0x24/0x98)
[ 5928.123882] [] (clk_gate_endisable) from [] (clk_core_disable+0x60/0x84)
[ 5928.132299] [] (clk_core_disable) from [] (clk_disable+0x24/0x30)
[ 5928.140117] [] (clk_disable) from [] (s5p_mfc_handle_frame+0x254/0x860)
[ 5928.148445] [] (s5p_mfc_handle_frame) from [] (s5p_mfc_irq+0x890/0xa24)
[ 5928.156778] [] (s5p_mfc_irq) from [] (handle_irq_event_percpu+0x50/0x14c)
[ 5928.165283] [] (handle_irq_event_percpu) from [] (handle_irq_event+0x38/0x5c)
[ 5928.174143] [] (handle_irq_event) from [] (handle_fasteoi_irq+0xdc/0x1a4)
[ 5928.182645] [] (handle_fasteoi_irq) from [] (generic_handle_irq+0x18/0x28)
[ 5928.191236] [] (generic_handle_irq) from [] (__handle_domain_irq+0x6c/0xdc)
[ 5928.199917] [] (__handle_domain_irq) from [] (gic_handle_irq+0x4c/0x98)
[ 5928.208249] [] (gic_handle_irq) from [] (__irq_svc+0x54/0x90)
[ 5928.215709] Exception stack(0xeddb5cb8 to 0xeddb5d00)
[ 5928.220745] 5ca0:                                                       ee80454c faddfadc
[ 5928.228906] 5cc0: 00000000 01000001 ee831ce0 f8114200 ee807c00 01130520 00000403 eddb5d84
[ 5928.237063] 5ce0: ee807c48 2faf0800 ee807c0c eddb5d08 c046b618 c046b634 20000053 ffffffff
[ 5928.245225] [] (__irq_svc) from [] (exynos_cpuclk_notifier_cb+0x170/0x270)
[ 5928.253823] [] (exynos_cpuclk_notifier_cb) from [] (notifier_call_chain+0x44/0x84)
[ 5928.263106] [] (notifier_call_chain) from [] (__srcu_notifier_call_chain+0x6c/0x9c)
[ 5928.272480] [] (__srcu_notifier_call_chain) from [] (srcu_notifier_call_chain+0x18/0x20)
[ 5928.282288] [] (srcu_notifier_call_chain) from [] (__clk_notify+0x6c/0x74)
[ 5928.290881] [] (__clk_notify) from [] (clk_propagate_rate_change+0xa0/0xac)
[ 5928.299561] [] (clk_propagate_rate_change) from [] (clk_propagate_rate_change+0x90/0xac)
[ 5928.309370] [] (clk_propagate_rate_change) from [] (clk_core_set_rate_nolock+0x64/0xa8)
[ 5928.319091] [] (clk_core_set_rate_nolock) from [] (clk_set_rate+0x20/0x30)
[ 5928.327686] [] (clk_set_rate) from [] (set_target+0xe8/0x23c)
[ 5928.335152] [] (set_target) from [] (__cpufreq_driver_target+0x184/0x29c)
[ 5928.343655] [] (__cpufreq_driver_target) from [] (cpufreq_set+0x44/0x64)
[ 5928.352074] [] (cpufreq_set) from [] (store_scaling_setspeed+0x5c/0x74)
[ 5928.360407] [] (store_scaling_setspeed) from [] (store+0x7c/0x98)
[ 5928.368221] [] (store) from [] (sysfs_kf_write+0x44/0x48)
[ 5928.375338] [] (sysfs_kf_write) from [] (kernfs_fop_write+0xb8/0x1bc)
[ 5928.383496] [] (kernfs_fop_write) from [] (__vfs_write+0x2c/0xd4)
[ 5928.391308] [] (__vfs_write) from [] (vfs_write+0xa0/0x144)
[ 5928.398598] [] (vfs_write) from [] (SyS_write+0x44/0x84)
[ 5928.405631] [] (SyS_write) from [] (ret_fast_syscall+0x0/0x3c)

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2015-12-13T00:43:44+00:00

Pull ARM SoC fixes from Arnd Bergmann:
 "Here are a bunch of small bug fixes for various ARM platforms, nothing
  really sticks out this week, most of either fixes bugs in code that
  was just added in 4.4, or that has been broken for many years without
  anyone noticing.

  at91/sama5d2:
   - fix sama5de hardware setup of sd/mmc interface
   - proper selection of pinctrl drivers.  PIO4 is necessary for sama5d2

  berlin:
   - fix incorrect clock input for SDIO

  exynos:
   - Fix potential NULL pointer dereference in Exynos PMU driver.

  imx:
   - Fix vf610 SAI clock configuration bug which is discovered by the
     newly added master mode support in SAI audio driver.
   - Fix buggy L2 cache latency values in vf610 device trees, which may
     cause system hang when cpu runs at a higher frequency.

  ixp4xx:
   - fix prototypes for readl/writel functions

  ls2080a:
   - use little-endian register access for GPIO and SDHCI

  omap:
   - Fix clock source for ARM TWD and global timers on am437x
   - Always select REGULATOR_FIXED_VOLTAGE for omap2+ instead of when
     MACH_OMAP3_PANDORA is selected
   - Fix SPI DMA handles for dm816x as only some were mapped
   - Fix up mbox cells for dm816x to make mailbox usable

  pxa:
   - use PWM lookup table for all ezx machines

  s3c24xx:
   - Remove incorrect __init annotation from s3c24xx cpufreq driver
     structures.

  versatile:
   - fix PCI IRQ mapping on Versatile PB"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ls2080a/dts: Add little endian property for GPIO IP block
  dt-bindings: define little-endian property for QorIQ GPIO
  ARM64: dts: ls2080a: fix eSDHC endianness
  ARM: dts: vf610: use reset values for L2 cache latencies
  ARM: pxa: use PWM lookup table for all machines
  ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1
  ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock
  ARM: dts: am4372: fix clock source for arm twd and global timers
  ARM: at91: fix pinctrl driver selection
  ARM: at91/dt: add always-on to 1.8V regulator
  ARM: dts: vf610: fix clock definition for SAI2
  ARM: imx: clk-vf610: fix SAI clock tree
  ARM: ixp4xx: fix read{b,w,l} return types
  irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB
  ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE
  ARM: dts: add dm816x missing spi DT dma handles
  ARM: dts: add dm816x missing #mbox-cells
  cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init
  ARM: EXYNOS: Fix potential NULL pointer access in exynos_sys_powerdown_conf

clk: sunxi: pll2: Fix clock running too fast

2015-12-03T07:27:47+00:00

Contrary to what the datasheet says, the pre divider doesn't seem to be
incremented by one in the PLL2, but just uses the value from the register,
with 0 being a bypass.

This fixes the audio playing too fast.

Since we now have the same pre-divider flags, and the only difference with
the A10 is the post-divider offset, also remove the structure to just pass
the offset as an argument.

Signed-off-by: Maxime Ripard 
Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support")
Signed-off-by: Stephen Boyd

ARM: imx: clk-vf610: fix SAI clock tree

2015-12-02T01:46:26+00:00

The Synchronous Audio Interface (SAI) instances are clocked by
independent clocks: The bus clock and the audio clock (as shown in
Figure 51-1 in the Vybrid Reference Manual). The clock gates in
CCGR0/CCGR1 for SAI0 through SAI3 are bus clock gates, as access
tests to the registers with/without gating those clocks have shown.
The audio clock is gated by the SAIx_EN gates in CCM_CSCDR1,
followed by a clock divider (SAIx_DIV). Currently, the parent of
the bus clock gates has been assigned to SAIx_DIV, which is not
involved in the bus clock path for the SAI instances (see chapter
9.10.12, SAI clocking in the Vybrid Reference Manual).

Fix this by define the parent clock of VF610_CLK_SAIx to be the bus
clock.

If the driver needs the audio clock (when used in master mode), a
fixed device tree is required which assign the audio clock properly
to VF610_CLK_SAIx_DIV.

Signed-off-by: Stefan Agner 
Acked-by: Stephen Boyd 
Signed-off-by: Shawn Guo