linux-stable.git/drivers/clk, branch v4.4.31

clk: divider: Fix clk_divider_round_rate() to use clk_readl()

2016-10-31T10:14:01+00:00

commit 2cf9a57811bddb6fa6b0f8d7376da164d5534813 upstream.

clk-divider uses clk_readl()/clk_writel() everywhere, except in
clk_divider_round_rate(), where plain readl() is used. Change this to
clk_readl(), as it makes a difference on powerpc.

Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: James Hogan 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qoriq: fix a register offset error

2016-10-31T10:14:01+00:00

commit 8964193f6bfda5c4cf14eedb7e94892c1f1c34f0 upstream.

The offset of Core Cluster clock control/status register
on cluster group V3 version is different from others, and
should be plus 0x70000.

Signed-off-by: Tang Yuantian 
Reviewed-by: Scott Wood 
Fixes: 9e19ca2f627e ("clk: qoriq: Add ls2080a support.")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

ARM: clk-imx35: fix name for ckil clk

2016-10-31T10:13:59+00:00

commit fcff03813a7c612873303037cef5ba0329850c35 upstream.

This fixes
	[    0.000000] i.MX clk 82: register failed with -17
because the name is duplicated.

Signed-off-by: Uwe Kleine-König 
Fixes: 3713e3f5e927 ("clk: imx35: define two clocks for rtc")
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: imx6: initialize GPU clocks

2016-10-28T07:01:26+00:00

commit d8846023aed1293e54d33499558fc2aa2b2f393f upstream.

Initialize the GPU clock muxes to sane inputs. Until now they have
not been changed from their default values, which means that both
GPU3D shader and GPU2D core were fed by clock inputs whose rates
exceed the maximium allowed frequency of the cores by as much as
200MHz.

This fixes a severe GPU stability issue on i.MX6DL.

Signed-off-by: Lucas Stach 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: xgene: Add missing parenthesis when clearing divider value

2016-10-07T13:23:47+00:00

commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 upstream.

In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho 
Acked-by: Toan Le 
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: xgene: Fix divider with non-zero shift value

2016-09-15T06:27:39+00:00

[ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ]

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho 
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: initialize flags of clk_init_data in mmc-phase clock

2016-08-10T09:49:28+00:00

commit 595144c1141c951a3c6bb9004ae6a2bc29aad66f upstream.

The flags element of clk_init_data was never initialized for mmc-
phase-clocks resulting in the element containing a random value
and thus possibly enabling unwanted clock flags.

Fixes: 89bf26cbc1a0 ("clk: rockchip: Add support for the mmc clock phases using the framework")
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: divider value has to be 1 or more

2016-06-08T01:14:35+00:00

commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e upstream.

Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: pll_off should only update CM_PLL_ANARST

2016-06-08T01:14:34+00:00

commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06 upstream.

bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: at91: fix check of clk_register() returned value

2016-06-08T01:14:34+00:00

commit cb0ceaf77d93964a0d00477c79f4499123f6159c upstream.

The clk_register() function returns a valid pointer to struct clk or
ERR_PTR() error code, this makes a check for returned NULL value
useless and may lead to oops on error path.

Signed-off-by: Vladimir Zapolskiy 
Acked-by: Alexandre Belloni 
Acked-by: Boris Brezillon 
Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman