linux-stable.git/drivers/clk, branch v4.4.181

clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider

2019-06-11T10:23:45+00:00

commit 40db569d6769ffa3864fd1b89616b1a7323568a8 upstream.

There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.

Cc: 
Tested-by: Steev Klimaszewski 
Signed-off-by: Dmitry Osipenko 
Acked-By: Peter De Schrijver 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: ingenic: Fix round_rate misbehaving with non-integer dividers

2019-03-23T07:44:36+00:00

commit bc5d922c93491878c44c9216e9d227c7eeb81d7f upstream.

Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz.
This results in a theorical divider of 41.999993 which is then rounded
up to 42. The .round_rate function would then return (180 MHz / 42) as
the clock, rounded down, so 4.285714 MHz.

Calling clk_set_rate on 4.285714 MHz would round the rate again, and
give a theorical divider of 42,0000028, now rounded up to 43, and the
rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not
what we requested.

Fix this by rounding up the divisions.

Signed-off-by: Paul Cercueil 
Tested-by: Maarten ter Huurne 
Cc: 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: imx6sl: ensure MMDC CH0 handshake is bypassed

2019-02-20T09:13:08+00:00

[ Upstream commit 0efcc2c0fd2001a83240a8c3d71f67770484917e ]

Same as other i.MX6 SoCs, ensure unused MMDC channel's
handshake is bypassed, this is to make sure no request
signal will be generated when periphe_clk_sel is changed
or SRC warm reset is triggered.

Signed-off-by: Anson Huang 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: imx6q: reset exclusive gates on init

2019-01-26T08:42:53+00:00

[ Upstream commit f7542d817733f461258fd3a47d77da35b2d9fc81 ]

The exclusive gates may be set up in the wrong way by software running
before the clock driver comes up. In that case the exclusive setup is
locked in its initial state, as the complementary function can't be
activated without disabling the initial setup first.

To avoid this lock situation, reset the exclusive gates to the off
state and allow the kernel to provide the proper setup.

Signed-off-by: Lucas Stach 
Reviewed-by: Dong Aisheng 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: mmp: Off by one in mmp_clk_add()

2018-12-21T13:09:53+00:00

[ Upstream commit 2e85c57493e391b93445c1e0d530b36b95becc64 ]

The > comparison should be >= or we write one element beyond the end of
the unit->clk_table[] array.

(The unit->clk_table[] array is allocated in the mmp_clk_init() function
and it has unit->nr_clks elements).

Fixes: 4661fda10f8b ("clk: mmp: add basic support functions for DT support")
Signed-off-by: Dan Carpenter 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: samsung: exynos5420: Enable PERIS clocks for suspend

2018-11-27T15:08:00+00:00

[ Upstream commit b33228029d842269e17bba591609e83ed422005d ]

Ensure that clocks for core SoC modules (including TZPC0..9 modules)
are enabled for suspend/resume cycle. This fixes suspend/resume
support on Exynos5422-based Odroid XU3/XU4 boards.

Suggested-by: Joonyoung Shim 
Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Sasha Levin

clk: s2mps11: Fix matching when built as module and DT node contains compatible

2018-11-21T08:27:41+00:00

commit 8985167ecf57f97061599a155bb9652c84ea4913 upstream.

When driver is built as module and DT node contains clocks compatible
(e.g. "samsung,s2mps11-clk"), the module will not be autoloaded because
module aliases won't match.

The modalias from uevent: of:NclocksTCsamsung,s2mps11-clk
The modalias from driver: platform:s2mps11-clk

The devices are instantiated by parent's MFD.  However both Device Tree
bindings and parent define the compatible for clocks devices.  In case
of module matching this DT compatible will be used.

The issue will not happen if this is a built-in (no need for module
matching) or when clocks DT node does not contain compatible (not
correct from bindings perspective but working for driver).

Note when backporting to stable kernels: adjust the list of device ID
entries.

Cc: 
Fixes: 53c31b3437a6 ("mfd: sec-core: Add of_compatible strings for clock MFD cells")
Signed-off-by: Krzysztof Kozlowski 
Acked-by: Stephen Boyd 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: imx6ul: fix missing of_node_put()

2018-09-26T06:35:05+00:00

[ Upstream commit 11177e7a7aaef95935592072985526ebf0a3df43 ]

of_find_compatible_node() is returning a device node with refcount
incremented and must be explicitly decremented after the last use
which is right after the us in of_iomap() here.

Signed-off-by: Nicholas Mc Guire 
Fixes: 787b4271a6a0 ("clk: imx: add imx6ul clk tree support")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

clk: tegra: Fix PLL_U post divider and initial rate on Tegra30

2018-07-25T08:18:32+00:00

commit 797097301860c64b63346d068ba4fe4992bd5021 upstream.

The post divider value in the frequency table is wrong as it would lead
to the PLL producing an output rate of 960 MHz instead of the desired
480 MHz. This wasn't a problem as nothing used the table to actually
initialize the PLL rate, but the bootloader configuration was used
unaltered.

If the bootloader does not set up the PLL it will fail to come when used
under Linux. To fix this don't rely on the bootloader, but set the
correct rate in the clock driver.

Signed-off-by: Lucas Stach 
Signed-off-by: Thierry Reding 
[jonathanh@nvidia.com: Back-ported to stable v4.4.y]
Signed-off-by: Jon Hunter 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos3250: Fix PLL rates

2018-05-30T05:49:16+00:00

[ Upstream commit a8321e7887410a2b2e80ab89d1ef7b30562658ea ]

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. If that is not the case, rate of the PLL's child clock
might be set not as expected. For instance, if in the PLL rates table we have
a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
will return 393216003. If we now attempt to set rate of a PLL's child divider
clock to 393216000/2 its rate will be 131072001, rather than 196608000.
That is, the divider will be set to 3 instead of 2, because 393216003/2 is
greater than 196608000.

To fix this issue declared rates are changed to exactly match rates generated
by the PLL, as calculated from the P, M, S, K coefficients.

In this patch an erroneous P value for 74176002 output frequency is also
corrected.

Signed-off-by: Andrzej Hajda 
Acked-by: Chanwoo Choi 
Acked-by: Tomasz Figa 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman