linux-stable.git/drivers/clk, branch v4.20.2

clk: sunxi-ng: Use u64 for calculation of NM rate

2019-01-09T16:45:58+00:00

commit 65b6657672388b72822e0367f06d41c1e3ffb5bb upstream.

Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
rate is 24MHz, intermediate result when calculating final rate easily
overflows 32 bit variable.

Because of that, introduce function for calculating clock rate which
uses 64 bit variable for intermediate result.

Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
Fixes: ee28648cb2b4 ("clk: sunxi-ng: Remove the use of rational computations")

CC: 
Signed-off-by: Jernej Skrabec 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: fix typo in rk3188 spdif_frac parent

2019-01-09T16:45:58+00:00

commit 8b19faf6fae2867e2c177212c541e8ae36aa4d32 upstream.

Fix typo in common_clk_branches.
Make spdif_pre parent of spdif_frac.

Fixes: 667464208989 ("clk: rockchip: include downstream muxes into fractional dividers")
Cc: stable@vger.kernel.org
Signed-off-by: Johan Jonker 
Acked-by: Elaine Zhang 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: qcs404: Fix gpll0_out_main parent

2018-12-10T19:31:30+00:00

gpll0_out_main parent is cxo so fix it.

Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Signed-off-by: Srinivas Kandagatla 
Reviewed-by: Bjorn Andersson 
Signed-off-by: Vinod Koul 
Signed-off-by: Stephen Boyd

clk: zynqmp: Off by one in zynqmp_is_valid_clock()

2018-12-03T17:54:48+00:00

The > comparison should be >= to prevent reading beyond the end of the
clock[] array.

(The clock[] array is allocated in zynqmp_clk_setup() and has
clock_max_idx elements.)

Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Dan Carpenter 
Signed-off-by: Stephen Boyd

clk: mmp: Off by one in mmp_clk_add()

2018-12-03T17:54:48+00:00

The > comparison should be >= or we write one element beyond the end of
the unit->clk_table[] array.

(The unit->clk_table[] array is allocated in the mmp_clk_init() function
and it has unit->nr_clks elements).

Fixes: 4661fda10f8b ("clk: mmp: add basic support functions for DT support")
Signed-off-by: Dan Carpenter 
Signed-off-by: Stephen Boyd

clk: mvebu: Off by one bugs in cp110_of_clk_get()

2018-12-03T17:54:48+00:00

These > comparisons should be >= to prevent reading beyond the end of
of the clk_data->hws[] buffer.

The clk_data->hws[] array is allocated in cp110_syscon_common_probe()
when we do:
	cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) +
				      sizeof(struct clk_hw *) * CP110_CLK_NUM,
				      GFP_KERNEL);
As you can see, it has CP110_CLK_NUM elements which is equivalent to
CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS.

Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system controller")
Signed-off-by: Dan Carpenter 
Signed-off-by: Stephen Boyd

Merge branch 'clk-protected-binding' into clk-fixes

2018-11-28T06:33:58+00:00

* clk-protected-binding:
  clk: qcom: Support 'protected-clocks' property
  dt-bindings: clk: Introduce 'protected-clocks' property

clk: qcom: Support 'protected-clocks' property

2018-11-21T08:59:28+00:00

Certain firmware configurations "protect" clks and cause the entire
system to reboot when a non-secure OS such as Linux tries to read or
write protected clk registers. But other firmware configurations allow
reading or writing the same registers, and they may actually require
that the OS use the otherwise locked down clks. Support the
'protected-clocks' property by never registering these protected clks
with the common clk framework. This way, when firmware is protecting
these clks we won't have the chance to ever read or write these
registers and take down the entire system.

Cc: Taniya Das 
Cc: Bjorn Andersson 
Signed-off-by: Stephen Boyd 
Reviewed-by: Bjorn Andersson 
Signed-off-by: Stephen Boyd

clk: zynqmp: handle fixed factor param query error

2018-11-14T22:29:36+00:00

Return proper error code in case query for fixed factor
parameter fails. This also fixes build warning for set
but not used variable 'ret'.

Signed-off-by: Rajan Vaja 
Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Stephen Boyd

clk: qcom: gcc: Fix board clock node name

2018-11-09T22:13:55+00:00

Device tree node name are not supposed to have "_" in them so fix the
node name use of xo_board to xo-board

Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Signed-off-by: Vinod Koul 
Signed-off-by: Stephen Boyd