linux-stable.git/drivers/clk, branch v4.2.1

clk: qcom: Fix MSM8916 prng clock enable bit

2015-09-21T17:10:48+00:00

commit 1c4b4b0eb1909010b8ebda1ef208bf3ed62e7487 upstream.

Fix the enable bit of the pseudorandom number generator clock.

Reported-by: Stanimir Varbanov 
Fixes: 3966fab8b6ab "clk: qcom: Add MSM8916 Global Clock Controller support"
Signed-off-by: Georgi Djakov 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks

2015-09-21T17:10:48+00:00

commit d7a304e9d018c99dda80f4c16ec0fe817b5be4a1 upstream.

The other ce clocks have the flag set, but ce1 doesn't, so
clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
Set the flag as this is supported.

Reported-by: Bjorn Andersson 
Tested-by: Bjorn Andersson 
Fixes: 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes: d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: pxa: fix core frequency reporting unit

2015-09-21T17:10:48+00:00

commit 4b5fb7dc9096d949a22651370bb6bf11f21edb30 upstream.

Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely
on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency.

This reporting was broken because the expected unit is kHz and not
Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx.

Fixes: fe7710fae477 ("clk: add pxa25x clock drivers")
Fixes: d40670dc6169 ("clk: add pxa27x clock drivers")
Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
Signed-off-by: Robert Jarzmik 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: versatile: off by one in clk_sp810_timerclken_of_get()

2015-09-21T17:10:48+00:00

commit 3294bee87091be5f179474f6c39d1d87769635e2 upstream.

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter 
Acked-by: Pawel Moll 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: pistachio: correct critical clock list

2015-09-21T17:10:47+00:00

commit d31ff5f7f3b142b8d1ebb3da89187c54cdf2bc71 upstream.

Current critical clock list for pistachio enables
only mips and sys clocks by default but there are
also other clocks that are not claimed by anyone and
needs to be enabled by default.

This patch updates the critical clocks that need
to be enabled by default.

Add a separate struct to distinguish the critical clocks
as listed:
1.) core clocks:
	a.) mips clock
2.) peripheral system clocks:
	a.) sys clock
	b.) sys_bus clock
	c.) DDR clock
	d.) ROM clock

Fixes: b35d7c33419c("CLK: Pistachio: Register core clocks")
Reviewed-by: Andrew Bresticker 
Signed-off-by: Ezequiel Garcia 
Signed-off-by: Damien.Horsley 
Signed-off-by: Govindraj Raja 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: pistachio: Fix PLL rate calculation in integer mode

2015-09-21T17:10:47+00:00

commit 7937c6c57e0da7bffa7b10bac23f230c77523e35 upstream.

.recalc_rate callback for the fractional PLL doesn't take operating
mode into account when calculating PLL rate. This results in
the incorrect PLL rates when PLL is operating in integer mode.

Operating mode of fractional PLL is based on the value of the
fractional divider. Currently it assumes that the PLL will always
be configured in fractional mode which may not be
the case. This may result in the wrong output frequency.

Also vco was calculated based on the current operating mode which
makes no sense because .set_rate is setting operating mode. Instead,
vco should be calculated using PLL settings that are about to be set.

Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Reviewed-by: Andrew Bresticker 
Signed-off-by: Zdenko Pulitika 
Signed-off-by: Govindraj Raja 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: pistachio: Fix override of clk-pll settings from boot loader

2015-09-21T17:10:47+00:00

commit e53f21c761d141bbcbce06e9ddab3b4e0a828f2c upstream.

PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.

PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.

This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.

Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Reviewed-by: Andrew Bresitcker 
Signed-off-by: Zdenko Pulitika 
Signed-off-by: Govindraj Raja 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: pistachio: Fix 32bit integer overflows

2015-09-21T17:10:47+00:00

commit 093affb009a3d87848e51217cd1a06ce1135633f upstream.

This commit fixes 32bit integer overflows throughout the pll driver
(i.e. wherever the result of integer multiplication may exceed the
range of u32).

One of the functions affected by this problem is .recalc_rate. It
returns incorrect rate for some pll settings (not for all though)
which in turn results in the incorrect rate setup of pll's child
clocks.

Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Reviewed-by: Andrew Bresticker 
Signed-off-by: Zdenko Pulitika 
Signed-off-by: Govindraj Raja 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: s5pv210: add missing call to samsung_clk_of_add_provider()

2015-09-21T17:10:47+00:00

commit ba30011577330b7e29ecb5916d89c6db9fbc5b3d upstream.

Commit d5e136a21b2028fb1f45143ea7112d5869bfc6c7 ("clk: samsung: Register
clk provider only after registering its all clocks", merged to v3.17-rc1)
modified a way that driver registers registers to core framework. This
change has not been applied to s5pv210 clocks driver, which has been
merged in parallel to that commit. This patch adds a missing call to
samsung_clk_of_add_provider(), so the driver is operational again.

Signed-off-by: Marek Szyprowski 
Acked-by: Tomasz Figa 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: exynos4: Fix wrong clock for Exynos4x12 ADC

2015-09-21T17:10:46+00:00

commit e323d56eb06b266b77c2b430cb5f1977ba549e03 upstream.

The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
   ERROR: could not get clock /adc@126C0000:adc(0)
   exynos-adc 126c0000.adc: failed getting clock, err = -2
   exynos-adc: probe of 126c0000.adc failed with error -2

Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.

The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).

Signed-off-by: Krzysztof Kozlowski 
Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Reviewed-by: Javier Martinez Canillas 
Acked-by: Tomasz Figa 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman