linux-stable.git/drivers/clk, branch v4.19.86

clk: samsung: Use clk_hw API for calling clk framework from clk notifiers

2019-11-24T07:20:23+00:00

[ Upstream commit 1da220e3a5d22fccda0bc8542997abc1d1741268 ]

clk_notifier_register() documentation states, that the provided notifier
callbacks associated with the notifier must not re-enter into the clk
framework by calling any top-level clk APIs. Fix this by replacing
clk_get_rate() calls with clk_hw_get_rate(), which is safe in this
context.

Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Sasha Levin

clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420

2019-11-24T07:20:22+00:00

[ Upstream commit d32dd2a1a0f80edad158c9a1ba5f47650d9504a0 ]

The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on
exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to
handle the bit only on exynos5420.

Signed-off-by: Joonyoung Shim 
[m.szyprow: rewrote commit subject]
Signed-off-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Sasha Levin

clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume

2019-11-24T07:20:22+00:00

[ Upstream commit 70da9ee80228e6d98fd68e3c1db124c4461d283c ]

SoC clock drivers should suspend after every other drivers in the system,
which are using clocks and resume before them. The last stage for calling
suspend device callbacks is NOIRQ stage and there exists driver, which use
that state (dwmmc-exynos), so Exynos5433 clocks driver should also use it.
During the same stage, clocks driver will be always suspended after its
clients as a direct result of proper device probe order (deferred probe
reorders the suspend call sequence).

Signed-off-by: Marek Szyprowski 
Acked-by: Chanwoo Choi 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Sasha Levin

clk: keystone: Enable TISCI clocks if K3_ARCH

2019-11-24T07:19:48+00:00

[ Upstream commit 2f149e6e14bcb5e581e49307b54aafcd6f74a74f ]

K3_ARCH uses TISCI for clocks as well. Enable the same
for the driver support.

Signed-off-by: Nishanth Menon 
Acked-by: Santosh Shilimkar 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: sunxi-ng: h6: fix PWM gate/reset offset

2019-11-20T17:45:21+00:00

[ Upstream commit 58c0f79887d5e425fe6a9fd542778e50df69e9c6 ]

Currently the register offset of the PWM bus gate in Allwinner H6 clock
driver is wrong.

Fix this issue.

Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Rongyi Chen 
[Icenowy: refactor commit message]
Signed-off-by: Icenowy Zheng 
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Sasha Levin

clk: boston: unregister clks on failure in clk_boston_setup()

2019-11-06T12:05:26+00:00

[ Upstream commit 8b627f616ed63dcaf922369fc14a5daf8ad03038 ]

The registered clks should unregister when something wrong happens
before going out in function clk_boston_setup().

Signed-off-by: Yi Wang 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: sprd: add missing kfree

2019-10-07T16:57:03+00:00

[ Upstream commit 5e75ea9c67433a065b0e8595ad3c91c7c0ca0d2d ]

The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang 
Signed-off-by: Chunyan Zhang 
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: at91: select parent if main oscillator or bypass is enabled

2019-10-07T16:57:01+00:00

[ Upstream commit 69a6bcde7fd3fe6f3268ce26f31d9d9378384c98 ]

Selecting the right parent for the main clock is done using only
main oscillator enabled bit.
In case we have this oscillator bypassed by an external signal (no driving
on the XOUT line), we still use external clock, but with BYPASS bit set.
So, in this case we must select the same parent as before.
Create a macro that will select the right parent considering both bits from
the MOR register.
Use this macro when looking for the right parent.

Signed-off-by: Eugen Hristev 
Link: https://lkml.kernel.org/r/1568042692-11784-2-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni 
Reviewed-by: Claudiu Beznea 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: gcc-sdm845: Use floor ops for sdcc clks

2019-10-07T16:56:59+00:00

[ Upstream commit 5e4b7e82d497580bc430576c4c9bce157dd72512 ]

Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is because the clk ops for qcom clks round the
frequency up to the nearest rate instead of down to the nearest rate.
For example, the MMC driver requests a frequency of 52MHz from
clk_set_rate() but the qcom implementation for these clks rounds 52MHz
up to the next supported frequency of 100MHz. The MMC driver could be
modified to request clk rate ranges but for now we can fix this in the
clk driver by changing the rounding policy for this clk to be round down
instead of round up.

Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: Douglas Anderson 
Cc: Taniya Das 
Signed-off-by: Stephen Boyd 
Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org
Reviewed-by: Douglas Anderson 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain

2019-10-07T16:56:56+00:00

[ Upstream commit f787216f33ce5b5a2567766398f44ab62157114c ]

The CPG/MSSR Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

Note that this only affects RZ/A2 SoCs.  On R-Car Gen2 and Gen3 SoCs,
the R-Car SYSC driver handles Clock Domain creation, and offloads only
device attachment/detachment to the CPG/MSSR driver.

Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Reviewed-by: Ulf Hansson 
Signed-off-by: Sasha Levin