linux-stable.git/drivers/clk, branch v4.17.4

clk: at91: PLL recalc_rate() now using cached MUL and DIV values

2018-07-03T09:27:02+00:00

commit a982e45dc150da3a08907b6dd676b735391704b4 upstream.

When a USB device is connected to the USB host port on the SAM9N12 then
you get "-62" error which seems to indicate USB replies from the device
are timing out. Based on a logic sniffer, I saw the USB bus was running
at half speed.

The PLL code uses cached MUL and DIV values which get set in set_rate()
and applied in prepare(), but the recalc_rate() function instead
queries the hardware instead of using these cached values. Therefore,
if recalc_rate() is called between a set_rate() and prepare(), the
wrong frequency is calculated and later the USB clock divider for the
SAM9N12 SOC will be configured for an incorrect clock.

In my case, the PLL hardware was set to 96 Mhz before the OHCI
driver loads, and therefore the usb clock divider was being set
to /2 even though the OHCI driver set the PLL to 48 Mhz.

As an alternative explanation, I noticed this was fixed in the past by
87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL
driver") but the bug was later re-introduced by 1bdf02326b71 ("clk:
at91: make use of syscon/regmap internally").

Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally)
Cc: 
Signed-off-by: Marcin Ziemianowicz 
Acked-by: Boris Brezillon 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL

2018-07-03T09:27:02+00:00

commit 72e1f2302040398dafb64bbb93abdde78c1f2267 upstream.

Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we
relied on the bootloader to enable the fclk_div clock gates. It turns
out that our clock tree is incomplete at least on Meson8b (tested with
an Odroid-C1, which uses an RGMII PHY) because after the mentioned
commit Ethernet is not working anymore (no RX/TX activity can be seen).
At the same time Ethernet was still working on Meson8m2 with a RMII PHY.

Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops
working on Odroid-C1. Unfortunately it's currently not clear what the
Ethernet controller IP block uses the fclk_div2 clock for. Mark the
clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by
most bootloaders by default, which is why we didn't notice it before).

Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Cc: stable@vger.kernel.org
Signed-off-by: Martin Blumenstingl 
Tested-by: Kevin Hilman 
Signed-off-by: Jerome Brunet 
Signed-off-by: Greg Kroah-Hartman

clk:aspeed: Fix reset bits for PCI/VGA and PECI

2018-07-03T09:26:58+00:00

commit e76e56823a318ca580be4cfc5a6a9269bc70abea upstream.

This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.

Signed-off-by: Jae Hyun Yoo 
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: renesas: cpg-mssr: Stop using printk format %pCr

2018-07-03T09:26:48+00:00

commit ef4b0be62641d296cf4c0ad8f75ab83ab066ed51 upstream.

Printk format "%pCr" will be removed soon, as clk_get_rate() must not be
called in atomic context.

Replace it by open-coding the operation.  This is safe here, as the code
runs in task context.

Link: http://lkml.kernel.org/r/1527845302-12159-2-git-send-email-geert+renesas@glider.be
To: Jia-Ju Bai 
To: Jonathan Corbet 
To: Michael Turquette 
To: Stephen Boyd 
To: Zhang Rui 
To: Eduardo Valentin 
To: Eric Anholt 
To: Stefan Wahren 
To: Greg Kroah-Hartman 
Cc: Sergey Senozhatsky 
Cc: Petr Mladek 
Cc: Linus Torvalds 
Cc: Steven Rostedt 
Cc: linux-doc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Geert Uytterhoeven 
Cc: stable@vger.kernel.org # 4.5+
Signed-off-by: Geert Uytterhoeven 
Acked-by: Stephen Boyd 
Signed-off-by: Petr Mladek 
Signed-off-by: Greg Kroah-Hartman

clk: stm32: fix: stm32 clock drivers are not compiled by default

2018-05-15T22:47:03+00:00

Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depends on' commands, but 'def_bool'
with the machine(s).

Fixes: da32d3539fca ("clk: stm32: add configuration flags for each of the stm32 drivers")
Signed-off-by: Gabriel Fernandez 
Acked-by: Alexandre TORGUE 
Signed-off-by: Stephen Boyd

clk: imx6ull: use OSC clock during AXI rate change

2018-05-15T22:41:01+00:00

On i.MX6 ULL using PLL3 seems to cause a freeze when setting
the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
for busy divider and busy mux"), probably because the clock is
now forced to be on.

Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by: Stefan Agner 
Signed-off-by: Stephen Boyd

Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson into clk-fixes

2018-05-01T21:44:16+00:00

Pull meson clk fixes from Jerome Brunet:
 - fix typos in two meson8 clock names
 - remove unused clock ops declaration

* tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
  clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
  clk: meson: drop meson_aoclk_gate_regmap_ops

clk: meson: meson8b: fix meson8b_cpu_clk parent clock name

2018-04-25T08:23:19+00:00

meson8b_cpu_clk has two parent clocks:
- meson8b_xtal
- meson8b_cpu_scale_out_sel

The name of the "xtal" clock parent is specified correctly. However,
there is a typo in the name of the second parent clock. The
meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel"
(which matches the name from the datasheet). However, the mux parent
definition uses the name "cpu_out_sel" which does not match any existing
clock.

Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: meson8b: fix meson8b_fclk_div3_div clock name

2018-04-25T08:21:35+00:00

The names of all fclk divider gate clocks follow the naming schema
"fclk_divN" and the name of all fclk fixed dividers follow the naming
schema "fclk_divN_div".
There's one exception to this rule: meson8b_fclk_div3_div's name is
"fclk_div_div3". It's child clock meson8b_fclk_div3 however references
it as "fclk_div3_div" (following the naming schema explained above).

Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
schema. This also fixes serial console on my Meson8m2 board because
"clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
and all of it's children (UART clock, SDIO MMC controller clock, ...)
are all 0.

Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: drop meson_aoclk_gate_regmap_ops

2018-04-25T08:19:26+00:00

let's remove the unused meson_aoclk_gate_regmap_ops

Fixes: 1f932d99710d ("clk: meson: remove superseded aoclk_gate_regmap")
Signed-off-by: Yixun Lan 
Signed-off-by: Jerome Brunet