linux-stable.git/drivers/clk, branch v4.16.4

clk: tegra: Mark HCLK, SCLK and EMC as critical

2018-04-24T07:43:04+00:00

commit 2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4 upstream.

Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
as critical.

Signed-off-by: Dmitry Osipenko 
Acked-by: Peter De Schrijver 
Cc:  # v4.16
Signed-off-by: Thierry Reding 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: De-assert/assert PLL reset signal when appropriate

2018-04-24T07:43:04+00:00

commit 753872373b599384ac7df809aa61ea12d1c4d5d1 upstream.

In order to enable a PLL, not only the PLL has to be powered up and
locked, but you also have to de-assert the reset signal. The last part
was missing. Add it so PLLs that were not enabled by the FW/bootloader
can be enabled from Linux.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: 
Signed-off-by: Boris Brezillon 
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: mediatek: fix PWM clock source by adding a fixed-factor clock

2018-04-24T07:43:04+00:00

commit 89cd7aec21af26fd0c117bfc4bfc781724f201de upstream.

The clock for which all PWM devices on MT7623 or MT2701 actually depending
on has to be divided by four from its parent clock axi_sel in the clock
path prior to PWM devices.

Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
clock axi_sel allows that PWM devices can have the correct resolution
calculation.

Cc: stable@vger.kernel.org
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Sean Wang 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: fix false-positive Wmaybe-uninitialized warning

2018-04-24T07:43:04+00:00

commit ce33f284935e08229046b30635e6aadcbab02b53 upstream.

When we build this driver with on x86-32, gcc produces a false-positive warning:

drivers/clk/renesas/clk-sh73a0.c: In function 'sh73a0_cpg_clocks_init':
drivers/clk/renesas/clk-sh73a0.c:155:10: error: 'parent_name' may be used uninitialized in this function [-Werror=maybe-uninitialized]
   return clk_register_fixed_factor(NULL, name, parent_name, 0,

We can work around that warning by adding a fake initialization, I tried
and failed to come up with any better workaround. This is currently one
of few remaining warnings for a 4.14.y randconfig build, so it would be
good to also have it backported at least to that version. Older versions
have more randconfig warnings, so we might not care.

I had not noticed this earlier, because one patch in my randconfig test
tree removes the '-ffreestanding' option on x86-32, and that avoids
the warning. The -ffreestanding flag was originally global but moved
into arch/i386 by Andi Kleen in commit 6edfba1b33c7 ("[PATCH] x86_64:
Don't define string functions to builtin") as a 'temporary workaround'.

Like many temporary hacks, this turned out to be rather long-lived, from
all I can tell we still need a simple fix to asm/string_32.h before it
can be removed, but I'm not sure about how to best do that.

Cc: stable@vger.kernel.org
Cc: Andi Kleen 
Signed-off-by: Arnd Bergmann 
Acked-by: Geert Uytterhoeven 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: mvebu: armada-38x: add support for missing clocks

2018-04-24T07:43:04+00:00

commit 6a4a4595804548e173f0763a0e7274a3521c59a9 upstream.

Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
or 1333MHz (industrial).

They have also some dip-switches to select a different clock (666, 800,
1066, 1200).

The funny thing is that the recovery button is on the MPP34 fq selector.
So, when booting an industrial board with this button down, the frequency
666MHz is selected (and the kernel didn't boot).

This patch add all the missing clocks.

The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).

Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385")
Cc:  # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants
Cc:  # 3.16.x

Signed-off-by: Richard Genoud 
Acked-by: Gregory CLEMENT 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: Protect sections updating shared registers

2018-03-19T16:27:37+00:00

CM_PLLx and A2W_XOSC_CTRL registers are accessed by different clock
handlers and must be accessed with ->regs_lock held.
Update the sections where this protection is missing.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: 
Signed-off-by: Boris Brezillon 
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: bcm2835: Fix ana->maskX definitions

2018-03-19T16:27:23+00:00

ana->maskX values are already '~'-ed in bcm2835_pll_set_rate(). Remove
the '~' in the definition to fix ANA setup.

Note that this commit fixes a long standing bug preventing one from
using an HDMI display if it's plugged after the FW has booted Linux.
This is because PLLH is used by the HDMI encoder to generate the pixel
clock.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: 
Signed-off-by: Boris Brezillon 
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: aspeed: Prevent reset if clock is enabled

2018-03-15T18:13:49+00:00

According to the Aspeed specification, the reset and enable sequence
should be done when the clock is stopped. The specification doesn't
define behavior if the reset is done while the clock is enabled.

From testing on the AST2500, the LPC Controller has problems if the
clock is reset while enabled.

Therefore, check whether the clock is enabled or not before performing
the reset and enable sequence in the Aspeed clock driver.

Reported-by: Lei Yu 
Signed-off-by: Eddie James 
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Reviewed-by: Joel Stanley 
Signed-off-by: Stephen Boyd

clk: aspeed: Fix is_enabled for certain clocks

2018-03-15T18:11:43+00:00

Some of the Aspeed clocks are disabled by setting the relevant bit in
the "clock stop control" register to one, while others are disabled by
setting their bit to zero. The driver already uses a flag per gate  to
identify this behavior, but doesn't apply it in the clock is_enabled
function.

Use the existing gate flag to correctly return whether or not a clock
is enabled in the aspeed_clk_is_enabled function.

Signed-off-by: Eddie James 
Fixes: 6671507f0fbd ("clk: aspeed: Handle inverse polarity of USB port 1 clock gate")
Reviewed-by: Joel Stanley 
Signed-off-by: Stephen Boyd

clk: qcom: msm8916: Fix return value check in qcom_apcs_msm8916_clk_probe()

2018-03-12T22:14:24+00:00

In case of error, the function dev_get_regmap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: 81ac38847a1d ("clk: qcom: Add APCS clock controller support")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd