linux-stable.git/drivers/clk, branch v4.14.166

clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume

2020-01-17T18:45:48+00:00

commit e21be0d1d7bd7f78a77613f6bcb6965e72b22fc1 upstream.

Save and restore top PLL related configuration registers for big (APLL)
and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
were reset to default values after suspend/resume cycle and performance
after system resume was affected when performance governor has been selected.

Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")
Signed-off-by: Marian Mihailescu 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Greg Kroah-Hartman

clk: pxa: fix one of the pxa RTC clocks

2020-01-04T12:59:45+00:00

[ Upstream commit 46acbcb4849b2ca2e6e975e7c8130c1d61c8fd0c ]

The pxa27x platforms have a single IP with 2 drivers, sa1100-rtc and
rtc-pxa drivers.

A previous patch fixed the sa1100-rtc case, but the pxa-rtc wasn't
fixed. This patch completes the previous one.

Fixes: 8b6d10345e16 ("clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc")
Signed-off-by: Robert Jarzmik 
Link: https://lkml.kernel.org/r/20191026194420.11918-1-robert.jarzmik@free.fr
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: Allow constant ratio freq tables for rcg

2020-01-04T12:59:42+00:00

[ Upstream commit efd164b5520afd6fb2883b68e0d408a7de29c491 ]

Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just
some constant ratio from the input across the entire frequency range.  It
would be great if we could specify the frequency table as a single entry
constant ratio instead of a long list, ie:

	{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
        { }

So, lets support that.

We need to fix a corner case in qcom_find_freq() where if the freq table
is non-null, but has no frequencies, we end up returning an "entry" before
the table array, which is bad.  Then, we need ignore the freq from the
table, and instead base everything on the requested freq.

Suggested-by: Stephen Boyd 
Signed-off-by: Jeffrey Hugo 
Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: renesas: r8a77995: Correct parent clock of DU

2019-12-17T19:38:35+00:00

[ Upstream commit 515b2915ee08060ad4f6a3b3de38c5c2c5258e8b ]

According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car D3 is S1D1.

Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support")
Signed-off-by: Geert Uytterhoeven 
Acked-by: Stephen Boyd 
Reviewed-by: Laurent Pinchart 
Tested-by: Laurent Pinchart 
Signed-off-by: Sasha Levin

clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent

2019-12-17T19:38:32+00:00

[ Upstream commit 7bb7d29cffdd24bf419516d14b6768591e74069e ]

The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0.
Fix it.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Acked-by: Stephen Boyd 
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Sasha Levin

clk: rockchip: fix I2S1 clock gate register for rk3328

2019-12-17T19:37:57+00:00

[ Upstream commit 5c73ac2f8b70834a603eb2d92eb0bb464634420b ]

This patch fixes definition of I2S1 clock gate register for rk3328.
Current setting is not related I2S clocks.
  - bit6 of CRU_CLKGATE_CON0 means clk_ddrmon_en
  - bit6 of CRU_CLKGATE_CON1 means clk_i2s1_en

Signed-off-by: Katsuhiro Suzuki 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering

2019-12-17T19:37:49+00:00

[ Upstream commit ac8cb53829a6ba119082e067f5bc8fab3611ce6a ]

Similar to commit a9f0c0e56371 ("clk: rockchip: fix rk3188 sclk_smc
gate data") there is one other gate clock in the rk3188 clock driver
with a similar wrong ordering, the sclk_mac_lbtest. So fix it as well.

Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: rockchip: fix rk3188 sclk_smc gate data

2019-12-17T19:37:47+00:00

[ Upstream commit a9f0c0e563717b9f63b3bb1c4a7c2df436a206d9 ]

Fix sclk_smc gate data.
Change variable order, flags come before the register address.

Signed-off-by: Finley Xiao 
Signed-off-by: Johan Jonker 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: sunxi-ng: a64: Fix gate bit of DSI DPHY

2019-12-17T19:37:40+00:00

[ Upstream commit ee678706e46d0d185c27cc214ad97828e0643159 ]

DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.

Signed-off-by: Jagan Teki 
Acked-by: Stephen Boyd 
Signed-off-by: Maxime Ripard 
Signed-off-by: Sasha Levin

clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated()

2019-12-05T14:38:07+00:00

commit c1e4580a1d0ff510d56268c1fc7fcfeec366fe70 upstream.

Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it
easier to do it from code that is not parsing device tree.

Also, this fixes an issue where the resulting clk_hw can be dereferenced
before being tested for error.

Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate")
Signed-off-by: Alexandre Belloni 
Signed-off-by: Stephen Boyd 
Signed-off-by: Lee Jones 
Signed-off-by: Greg Kroah-Hartman