linux-stable.git/drivers/clk, branch v4.12.7

clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock

2017-08-11T15:33:53+00:00

commit 9735ee9e3cc3ba113ac96b0368ef3f1a73092a23 upstream.

The current CPU clock is missing the option to change the rate of its
parents, leading to improper rates calculated by cpufreq, and eventually
crashes.

Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
Reported-by: Kevin Hilman 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

2017-06-14T23:48:03+00:00

Allwinner clock fixes for 4.12

Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix

* tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM

2017-05-31T19:57:30+00:00

The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM

2017-05-31T19:57:27+00:00

The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

Merge tag 'meson-clk-fixes-for-4.12-rc2' of git://github.com/baylibre/clk-meson into clk-fixes

2017-05-25T21:11:11+00:00

KConfig fix:
- clk: meson: gxbb: fix build error without RESET_CONTROLLER

clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition

2017-05-25T21:04:19+00:00

AHB BIST gate is actually controlled with bit 7.

This bug was detected while trying to use the NAND controller which is
using the DMA engine to transfer data to the NAND.
Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
the core was disabling the DMA engine clock as part of its 'disable
unused clks' procedure, which was causing all DMA transfers to fail after
this point.

Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
Cc: stable@vger.kernel.org
Reported-by: Angus Ainslie 
Signed-off-by: Boris Brezillon 
Tested-by: Angus Ainslie 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Michael Turquette 
Link: lkml.kernel.org/r/1495643669-28221-1-git-send-email-boris.brezillon@free-electrons.com

clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM

2017-05-18T06:49:18+00:00

The newly added PRCM CCU driver uses SUNXI_CCU_MP_WITH_MUX_GATE, which causes
a link error when no other driver enables SUNXI_CCU_MP:

drivers/clk/built-in.o:(.data+0x5c8c8): undefined reference to `ccu_mp_ops'

This adds an explicit 'select' statement for it.

Signed-off-by: Arnd Bergmann 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: meson: gxbb: fix build error without RESET_CONTROLLER

2017-05-16T09:05:01+00:00

With CONFIG_RESET_CONTROLLER=n we see the following link error in the
meson gxbb clk driver:

drivers/built-in.o: In function 'gxbb_aoclkc_probe':
drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register'

Fix this by selecting the reset controller subsystem.

Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Signed-off-by: Tobias Regnery 
Acked-by: Neil Armstrong 
[narmstrong: Added fixes-by tag]
Signed-off-by: Neil Armstrong

clk: sunxi-ng: v3s: Fix usb otg device reset bit

2017-05-14T06:27:17+00:00

V3S's usb otg device reset bit should be 24, not 23.

Cc: stable@vger.kernel.org
Signed-off-by: Yong Deng 
Reviewed-By: Icenowy Zheng 
Signed-off-by: Maxime Ripard

clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

2017-05-14T06:27:17+00:00

The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: Bob Ham 
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: stable@vger.kernel.org # 4.9.x-
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard