linux-stable.git/drivers/clk, branch v4.1.6

clk: keystone: add support for post divider register for main pll

2015-08-17T03:52:17+00:00

commit 02fdfd708fd252a778709beb6c65d5e7360341ac upstream.

Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.

Signed-off-by: Murali Karicheri 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

drivers: clk: st: Incorrect register offset used for lock_status

2015-08-10T19:21:54+00:00

commit 56551da9255f20ffd3a9711728a1a3ad4b7100af upstream.

Incorrect register offset used for sthi407 clockgenC

Signed-off-by: Pankaj Dev 
Signed-off-by: Gabriel Fernandez 
Fixes: 51306d56ba81 ("clk: st: STiH407: Support for clockgenC0")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks

2015-08-10T19:21:54+00:00

commit 3be6d8ce639d92e60d144fb99dd74a53fe3799bb upstream.

This patch fixes the mux bit-setting for ClockgenA9.

Signed-off-by: Gabriel Fernandez 
Fixes: 13e6f2da1ddf ("clk: st: STiH407: Support for A9 MUX Clocks")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

drivers: clk: st: Fix flexgen lock init

2015-08-10T19:21:54+00:00

commit 0f4f2afd4402883a51ad27a1d9e046643bb1e3cb upstream.

While proving lock, the following warning happens
and it is fixed after initializing lock in the setup
function

INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33
[] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14)
[] (show_stack+0x10/0x14) from [] (__lock_acquire+0x900/0xb14)
[] (__lock_acquire+0x900/0xb14) from [] (lock_acquire+0x68/0x7c)
[] (lock_acquire+0x68/0x7c) from [] (_raw_spin_lock_irqsave+0x48/0x5c)
[] (_raw_spin_lock_irqsave+0x48/0x5c) from [] (clk_gate_endisable+0x28/0x88)
[] (clk_gate_endisable+0x28/0x88) from [] (clk_gate_enable+0xc/0x14)
[] (clk_gate_enable+0xc/0x14) from [] (flexgen_enable+0x28/0x40)
[] (flexgen_enable+0x28/0x40) from [] (__clk_enable+0x5c/0x9c)
[] (__clk_enable+0x5c/0x9c) from [] (clk_enable+0x18/0x2c)
[] (clk_enable+0x18/0x2c) from [] (st_lpc_of_register+0xc0/0x248)
[] (st_lpc_of_register+0xc0/0x248) from [] (clocksource_of_init+0x34/0x58)
[] (clocksource_of_init+0x34/0x58) from [] (sti_timer_init+0x10/0x18)
[] (sti_timer_init+0x10/0x18) from [] (time_init+0x20/0x30)
[] (time_init+0x20/0x30) from [] (start_kernel+0x20c/0x2e8)
[] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074)

Signed-off-by: Giuseppe Cavallaro 
Signed-off-by: Gabriel Fernandez 
Fixes: b116517055b7 ("clk: st: STiH407: Support for Flexgen Clocks")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Use parent rate when set rate to pixel RCG clock

2015-08-03T16:29:17+00:00

commit 6d451367bfa16fc103604bacd258f534c65d1540 upstream.

Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.

Signed-off-by: Hai Li 
Tested-by: Archit Taneja 
Fixes: 99cbd064b059 ("clk: qcom: Support display RCG clocks")
[sboyd@codeaurora.org: Silenced unused parent variable warning]
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: ti: dra7-atl-clock: Fix possible ERR_PTR dereference

2015-08-03T16:29:17+00:00

commit e0cdcda508f110b7ec190dc7c5eb2869ba73a535 upstream.

of_clk_get_from_provider() returns ERR_PTR on failure. The
dra7-atl-clock driver was not checking its return value and
immediately used it in __clk_get_hw().  __clk_get_hw()
dereferences supplied clock, if it is not NULL, so in that case
it would dereference an ERR_PTR.

Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: Fix JSON output in debugfs

2015-08-03T16:29:17+00:00

commit 7cb81136d2efe0f5ed9d965857f4756a15e6c338 upstream.

key/value pairs in a JSON object must be separated by a comma.
After adding the properties "accuracy" and "phase" the JSON output
of /sys/kernel/debug/clk/clk_dump is invalid.

So add the missing commas to fix it.

Fixes: 5279fc402ae5 ("clk: add clk accuracy retrieval support")
Signed-off-by: Stefan Wahren 
[sboyd@codeaurora.org: Added comment in function]
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

Merge branch 'ccf/atmel-fixes-for-4.1' of https://github.com/bbrezillon/linux-at91 into clk-fixes

2015-06-19T14:37:14+00:00

clk: at91: fix h32mx prototype inclusion in pmc header

2015-06-19T13:48:34+00:00

Trivial fix that prevents to compile this pmc clock driver if h32mx clock is
present but smd clock isn't.

Signed-off-by: Nicolas Ferre 
Signed-off-by: Boris Brezillon 
Acked-by: Alexandre Belloni 
Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock")
Cc:  # 3.18+

clk: at91: fix PERIPHERAL_MAX_SHIFT definition

2015-06-19T12:43:40+00:00

Fix the PERIPHERAL_MAX_SHIFT definition (3 instead of 4) and adapt the
round_rate and set_rate logic accordingly.

Signed-off-by: Boris Brezillon 
Reported-by: "Wu, Songjun"